Hello, and thank you for responding. В Срд, 23/01/2013 в 18:07 +0100, Roland Stigge пишет: > Hi Ilias, > > On 01/23/2013 11:47 AM, Ильяс Гасанов wrote: > > Package: magic > > Version: 7.5.229-1 > > Severity: important > > > > Dear Maintainer, > > > > I have detected an errant behavior at magic loadtime when process > > technology files are being parsed. Particularly, there are error > > messages about DRC rule syntax violations, for example: > > > > /usr/lib/x86_64-linux-gnu/magic/sys/scmos.tech: line 4493: > > section drc: > > Rule type "edge4way" usage: edge4way layers1 layers2 > > distance okTypes cornerTypes cornerDistance why [plane] > > /usr/lib/x86_64-linux-gnu/magic/sys/scmos.tech: line 4494: > > section drc: > > Bad DRC rule type "N-Well width must be at least 10 > > (MOSIS rule #1.1)" > > Valid rule types are: > > angles, edge, edge4way, exact_overlap, extend, no_overlap, > > overhang, rect_only, spacing, stepsize, surround, width, > > widespacing, area, maxwidth, cifstyle, cifwidth, cifspacing, > > cifarea, cifmaxwidth, rectangle. > > > > After that I have observed these files in /usr/lib/<arch>/magic/sys/ and > > diagnosed that they have redundant line breaks at logged positions. > > During the design process many design rule checks are not performed due > > to this. > > > > This issue has been detected in both Debian testing and experimental > > package trees. Furthermore, the files listed at magic official site do > > not have such syntax violations and work just ok: > > > > http://opencircuitdesign.com/magic/tech.html > > > > In the attachment there is a log extracted from wish stderr stream at > > magic startup. > > Thank you for your report! > > The upstream author already reported back that this is a known issue and > provided a fix. To test if it really solves the issue completely, I > would like to check your exact process. > > So can you please describe the complete actions w/ magic to reproduce > the issue? > > Thanks in advance, > > Roland
I started using magic in my study work only recently, so I can't yet figure out any specific details about this issue. As I said previously, the error messages appear at startup, while during the process certain DRC checks are not applied. For example, the size of borderspace around NMOS elements within n-well, as well as minimum distances between polysilicon and diffusion-to-metal contacts are not checked at all when those .tech files are loaded. What I did is I tried to reproduce the stuff from a lecture on YouTube, and also to do some experiments with more complex FET logic using irsim. Here is the video lecture which I was using in my work: http://www.youtube.com/watch?v=D32woicgdRk Sincerely, Ilyas Gasanov -- To UNSUBSCRIBE, email to debian-bugs-dist-requ...@lists.debian.org with a subject of "unsubscribe". Trouble? Contact listmas...@lists.debian.org
