[dpdk-dev] [PATCH v3 3/5] ixgbe: Config PFVML2FLT register

[Thomas Monjalon]

Title would be more high level.
Example: "ixgbe: configure Rx mode for VMDQ"

2014-10-31 13:19, Ouyang Changchun:
> +     for (i = 0; i < (int)num_pools; i++) {
> +             if (cfg->rx_mode & ETH_VMDQ_ACCEPT_UNTAG)
> +                     vmolr |= IXGBE_VMOLR_AUPE;
> +             if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_MC)
> +                     vmolr |= IXGBE_VMOLR_ROMPE;
> +             if (cfg->rx_mode & ETH_VMDQ_ACCEPT_HASH_UC)
> +                     vmolr |= IXGBE_VMOLR_ROPE;
> +             if (cfg->rx_mode & ETH_VMDQ_ACCEPT_BROADCAST)
> +                     vmolr |= IXGBE_VMOLR_BAM;
> +             if (cfg->rx_mode & ETH_VMDQ_ACCEPT_MULTICAST)
> +                     vmolr |= IXGBE_VMOLR_MPE;
> +
> +             IXGBE_WRITE_REG(hw, IXGBE_VMOLR(i), vmolr);
> +     }

Please factorize code with ixgbe_set_pool_rx_mode() which is really similar.

-- 
Thomas