Building with gcc 10.2 with SVE extension enabled got error: {standard input}: Assembler messages: {standard input}:91: Error: selected processor does not support `addvl x4,x8,#-1' {standard input}:95: Error: selected processor does not support `ptrue p1.d,all' {standard input}:135: Error: selected processor does not support `whilelo p2.d,xzr,x5' {standard input}:137: Error: selected processor does not support `decb x1'
This is because inline assembly code explicitly resets cpu model to not have SVE support. Thus SVE instructions generated by compiler auto vectorization got rejected by assembler. Fixed the issue by replacing inline assembly with equivalent atomic built-ins. Compiler will generate LSE instructions for cpu that has the extension. Fixes: f0c7bb1bf778 ("net/octeontx/base: add octeontx IO operations") Cc: jer...@marvell.com Cc: sta...@dpdk.org Signed-off-by: Ruifeng Wang <ruifeng.w...@arm.com> --- drivers/net/octeontx/base/octeontx_io.h | 16 ++++------------ 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/drivers/net/octeontx/base/octeontx_io.h b/drivers/net/octeontx/base/octeontx_io.h index 04b9ce191..0bf9b100d 100644 --- a/drivers/net/octeontx/base/octeontx_io.h +++ b/drivers/net/octeontx/base/octeontx_io.h @@ -58,14 +58,8 @@ do { \ static inline uint64_t octeontx_reg_ldadd_u64(void *addr, int64_t off) { - uint64_t old_val; - - __asm__ volatile( - " .cpu generic+lse\n" - " ldadd %1, %0, [%2]\n" - : "=r" (old_val) : "r" (off), "r" (addr) : "memory"); - - return old_val; + return (uint64_t)__atomic_fetch_add((int64_t *)addr, off, + __ATOMIC_RELAXED); } /** @@ -97,10 +91,8 @@ octeontx_reg_lmtst(void *lmtline_va, void *ioreg_va, const uint64_t cmdbuf[], } /* LDEOR initiates atomic transfer to I/O device */ - __asm__ volatile( - " .cpu generic+lse\n" - " ldeor xzr, %0, [%1]\n" - : "=r" (result) : "r" (ioreg_va) : "memory"); + result = __atomic_fetch_xor((uint64_t *)ioreg_va, 0, + __ATOMIC_RELAXED); } while (!result); } -- 2.25.1