The E830, E822 and E810 PTP initialization flows are similar. So
related fix are also added.
Signed-off-by: Paul Greenwalt <paul.greenw...@intel.com>
Signed-off-by: Sergey Temerkhanov <sergey.temerkha...@intel.com>
Signed-off-by: Qiming Yang <qiming.y...@intel.com>
---
drivers/net/ice/base/ice_ptp_hw.c | 295 +++++++++++++++++++-----------
drivers/net/ice/base/ice_ptp_hw.h | 94 +++++++++-
drivers/net/ice/base/ice_type.h | 18 +-
drivers/net/ice/ice_ethdev.c | 6 +-
4 files changed, 298 insertions(+), 115 deletions(-)
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index 43b7e313f4..a638bb114c 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -448,6 +448,17 @@ static void ice_ptp_clean_cmd(struct ice_hw *hw)
ice_flush(hw);
}
+/**
+ * ice_ptp_zero_syn_dlay - Set synchronization delay to zero
+ * @hw: pointer to HW struct
+ *
+ * Zero E810 and E830 specific PTP hardware clock synchronization delay.
+ */
+static void ice_ptp_zero_syn_dlay(struct ice_hw *hw)
+{
+ wr32(hw, GLTSYN_SYNC_DLAY, 0);
+ ice_flush(hw);
+}
/* ----------------------------------------------------------------------------
* E822 family functions
@@ -1037,6 +1048,33 @@ ice_clear_phy_tstamp_e822(struct ice_hw *hw, u8 quad, u8
idx)
return ICE_SUCCESS;
}
+/**
+ * ice_ptp_reset_ts_memory_quad_e822 - Clear all timestamps from the quad block
+ * @hw: pointer to the HW struct
+ * @quad: the quad to read from
+ *
+ * Clear all timestamps from the PHY quad block that is shared between the
+ * internal PHYs on the E822 devices.
+ */
+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad)
+{
+ ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
+ ice_write_quad_reg_e822(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M);
+}
+
+/**
+ * ice_ptp_reset_ts_memory_e822 - Clear all timestamps from all quad blocks
+ * @hw: pointer to the HW struct
+ */
+static void ice_ptp_reset_ts_memory_e822(struct ice_hw *hw)
+{
+ u8 quad;
+
+ for (quad = 0; quad < ICE_MAX_QUAD; quad++) {
+ ice_ptp_reset_ts_memory_quad_e822(hw, quad);
+ }
+}
+
/**
* ice_ptp_set_vernier_wl - Set the window length for vernier calibration
* @hw: pointer to the HW struct
@@ -2652,89 +2690,43 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port,
bool bypass)
}
/**
- * ice_phy_exit_bypass_e822 - Exit bypass mode, after vernier calculations
+ * ice_get_phy_tx_tstamp_ready_e822 - Read Tx memory status register
* @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * After hardware finishes vernier calculations for the Tx and Rx offset, this
- * function can be used to exit bypass mode by updating the total Tx and Rx
- * offsets, and then disabling bypass. This will enable hardware to include
- * the more precise offset calibrations, increasing precision of the generated
- * timestamps.
+ * @quad: the timestamp quad to read from
+ * @tstamp_ready: contents of the Tx memory status register
*
- * This cannot be done until hardware has measured the offsets, which requires
- * waiting until at least one packet has been sent and received by the device.
+ * Read the Q_REG_TX_MEMORY_STATUS register indicating which timestamps in
+ * the PHY are ready. A set bit means the corresponding timestamp is valid and
+ * ready to be captured from the PHY timestamp block.
*/
-enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port)
+static enum ice_status
+ice_get_phy_tx_tstamp_ready_e822(struct ice_hw *hw, u8 quad, u64 *tstamp_ready)
{
enum ice_status status;
- u32 val;
+ u32 hi, lo;
- status = ice_read_phy_reg_e822(hw, port, P_REG_TX_OV_STATUS, &val);
+ status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_U,
+ &hi);
if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_OV_STATUS for
port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U
for quad %u, status %d\n",
+ quad, status);
return status;
}
- if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
- ice_debug(hw, ICE_DBG_PTP, "Tx offset is not yet valid for port
%u\n",
- port);
- return ICE_ERR_NOT_READY;
- }
-
- status = ice_read_phy_reg_e822(hw, port, P_REG_RX_OV_STATUS, &val);
+ status = ice_read_quad_reg_e822(hw, quad, Q_REG_TX_MEMORY_STATUS_L,
+ &lo);
if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read RX_OV_STATUS for
port %u, status %d\n",
- port, status);
+ ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L
for quad %u, status %d\n",
+ quad, status);
return status;
}
- if (!(val & P_REG_TX_OV_STATUS_OV_M)) {
- ice_debug(hw, ICE_DBG_PTP, "Rx offset is not yet valid for port
%u\n",
- port);
- return ICE_ERR_NOT_READY;
- }
-
- status = ice_phy_cfg_tx_offset_e822(hw, port);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Tx offset
for port %u, status %d\n",
- port, status);
- return status;
- }
-
- status = ice_phy_cfg_rx_offset_e822(hw, port);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to program total Rx offset
for port %u, status %d\n",
- port, status);
- return status;
- }
-
- /* Exit bypass mode now that the offset has been updated */
- status = ice_read_phy_reg_e822(hw, port, P_REG_PS, &val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to read P_REG_PS for port
%u, status %d\n",
- port, status);
- return status;
- }
-
- if (!(val & P_REG_PS_BYPASS_MODE_M))
- ice_debug(hw, ICE_DBG_PTP, "Port %u not in bypass mode\n",
- port);
-
- val &= ~P_REG_PS_BYPASS_MODE_M;
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status) {
- ice_debug(hw, ICE_DBG_PTP, "Failed to disable bypass for port
%u, status %d\n",
- port, status);
- return status;
- }
-
- ice_info(hw, "Exiting bypass mode on PHY port %u\n", port);
+ *tstamp_ready = (u64)hi << 32 | (u64)lo;
return ICE_SUCCESS;
}
+
/* E810 functions
*
* The following functions operate on the E810 series devices which use
@@ -3218,6 +3210,22 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum
ice_ptp_tmr_cmd cmd,
return ICE_SUCCESS;
}
+/**
+ * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
+ * @hw: pointer to the HW struct
+ * @port: the PHY port to read
+ * @tstamp_ready: contents of the Tx memory status register
+ *
+ * E810 devices do not use a Tx memory status register. Instead simply
+ * indicate that all timestamps are currently ready.
+ */
+static enum ice_status
+ice_get_phy_tx_tstamp_ready_e810(struct ice_hw *hw, u8 port, u64 *tstamp_ready)
+{
+ *tstamp_ready = 0xFFFFFFFFFFFFFFFF;
+ return ICE_SUCCESS;
+}
+
/* E810T SMA functions
*
* The following functions operate specifically on E810T hardware and are used
@@ -3445,6 +3453,23 @@ bool ice_is_pca9575_present(struct ice_hw *hw)
return false;
}
+/* E830 functions
+ *
+ * The following functions operate on the E830 series devices.
+ *
+ */
+
+/**
+ * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
+ * @hw: pointer to HW struct
+ *
+ * Perform E830-specific PTP hardware clock initialization steps.
+ */
+static enum ice_status ice_ptp_init_phc_e830(struct ice_hw *hw)
+{
+ ice_ptp_zero_syn_dlay(hw);
+ return ICE_SUCCESS;
+}
/* Device agnostic functions
*
* The following functions implement shared behavior common to both E822/E823
@@ -3501,6 +3526,29 @@ void ice_ptp_unlock(struct ice_hw *hw)
wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0);
}
+#define ICE_DEVID_MASK 0xFFF8
+
+/**
+ * ice_ptp_init_phy_model - Initialize hw->phy_model based on device type
+ * @hw: pointer to the HW structure
+ *
+ * Determine the PHY model for the device, and initialize hw->phy_model
+ * for use by other functions.
+ */
+enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw)
+{
+
+ if (ice_is_e810(hw))
+ hw->phy_model = ICE_PHY_E810;
+ else if (ice_is_e830(hw))
+ hw->phy_model = ICE_PHY_E830;
+ else
+ hw->phy_model = ICE_PHY_E822;
+ hw->phy_ports = ICE_NUM_EXTERNAL_PORTS;
+
+ return ICE_SUCCESS;
+}
+
/**
* ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
* @hw: pointer to HW struct
@@ -3521,16 +3569,20 @@ ice_ptp_tmr_cmd(struct ice_hw *hw, enum ice_ptp_tmr_cmd
cmd, bool lock_sbq)
ice_ptp_src_cmd(hw, cmd);
/* Next, prepare the ports */
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_port_cmd_e810(hw, cmd, lock_sbq);
break;
case ICE_PHY_E822:
status = ice_ptp_port_cmd_e822(hw, cmd, lock_sbq);
break;
+ case ICE_PHY_E830:
+ status = ICE_SUCCESS;
+ break;
default:
status = ICE_ERR_NOT_SUPPORTED;
}
+
if (status) {
ice_debug(hw, ICE_DBG_PTP, "Failed to prepare PHY ports for
timer command %u, status %d\n",
cmd, status);
@@ -3577,13 +3629,16 @@ enum ice_status ice_ptp_init_time(struct ice_hw *hw,
u64 time,
/* PHY Clks */
/* Fill Rx and Tx ports and send msg to PHY */
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_prep_phy_time_e810(hw, time & 0xFFFFFFFF);
break;
case ICE_PHY_E822:
status = ice_ptp_prep_phy_time_e822(hw, time & 0xFFFFFFFF);
break;
+ case ICE_PHY_E830:
+ status = ICE_SUCCESS;
+ break;
default:
status = ICE_ERR_NOT_SUPPORTED;
}
@@ -3623,13 +3678,16 @@ enum ice_status ice_ptp_write_incval(struct ice_hw *hw,
u64 incval,
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), ICE_HI_DWORD(incval));
}
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_prep_phy_incval_e810(hw, incval);
break;
case ICE_PHY_E822:
status = ice_ptp_prep_phy_incval_e822(hw, incval);
break;
+ case ICE_PHY_E830:
+ status = ICE_SUCCESS;
+ break;
default:
status = ICE_ERR_NOT_SUPPORTED;
}
@@ -3693,7 +3751,7 @@ enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32
adj, bool lock_sbq)
wr32(hw, GLTSYN_SHADJ_L(tmr_idx), 0);
wr32(hw, GLTSYN_SHADJ_H(tmr_idx), adj);
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_e810(hw, adj, lock_sbq);
break;
@@ -3751,7 +3809,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time,
s32 adj)
wr32(hw, GLTSYN_SHTIME_H(tmr_idx), time_hi);
/* Prepare PHY port adjustments */
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_e810(hw, adj, true);
break;
@@ -3766,7 +3824,7 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time,
s32 adj)
return status;
/* Set target time for each PHY port */
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
status = ice_ptp_prep_phy_adj_target_e810(hw, time_lo);
break;
@@ -3797,49 +3855,58 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64
at_time, s32 adj)
enum ice_status
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp)
{
- enum ice_status status;
-
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
- status = ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
- break;
+ return ice_read_phy_tstamp_e810(hw, block, idx, tstamp);
case ICE_PHY_E822:
- status = ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
- break;
+ return ice_read_phy_tstamp_e822(hw, block, idx, tstamp);
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ return ICE_ERR_NOT_SUPPORTED;
}
-
- return status;
}
/**
- * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
+ * ice_clear_phy_tstamp - Drop a timestamp from the timestamp block
* @hw: pointer to the HW struct
* @block: the block to read from
* @idx: the timestamp index to reset
*
- * Clear a timestamp, resetting its valid bit, from the timestamp block. For
- * E822 devices, the block is the quad to clear from. For E810 devices, the
- * block is the logical port to clear from.
+ * Drop a timestamp from the timestamp block by reading it. This will reset
+ * the memory status bit allowing the timestamp index to be reused. For E822
+ * devices, the block is the quad to clear from. For E810 devices, the block
+ * is the logical port to clear from.
+ *
+ * This function should only be called on a timestamp index whose valid bit
+ * is set according to ice_get_phy_tx_tstamp_ready.
*/
enum ice_status
ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
{
- enum ice_status status;
-
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
- status = ice_clear_phy_tstamp_e810(hw, block, idx);
- break;
+ return ice_clear_phy_tstamp_e810(hw, block, idx);
case ICE_PHY_E822:
- status = ice_clear_phy_tstamp_e822(hw, block, idx);
- break;
+ return ice_clear_phy_tstamp_e822(hw, block, idx);
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ return ICE_ERR_NOT_SUPPORTED;
}
+}
- return status;
+/**
+ * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
+ * @hw: pointer to the HW struct
+ */
+void ice_ptp_reset_ts_memory(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E822:
+ ice_ptp_reset_ts_memory_e822(hw);
+ break;
+ case ICE_PHY_E810:
+ case ICE_PHY_E830:
+ default:
+ return;
+ }
}
/**
@@ -3850,7 +3917,6 @@ ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx)
*/
enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
{
- enum ice_status status;
u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned;
/* Enable source clocks */
@@ -3859,16 +3925,41 @@ enum ice_status ice_ptp_init_phc(struct ice_hw *hw)
/* Clear event status indications for auxiliary pins */
(void)rd32(hw, GLTSYN_STAT(src_idx));
- switch (hw->phy_cfg) {
+ switch (hw->phy_model) {
case ICE_PHY_E810:
- status = ice_ptp_init_phc_e810(hw);
- break;
+ return ice_ptp_init_phc_e810(hw);
case ICE_PHY_E822:
- status = ice_ptp_init_phc_e822(hw);
- break;
+ return ice_ptp_init_phc_e822(hw);
+ case ICE_PHY_E830:
+ return ice_ptp_init_phc_e830(hw);
default:
- status = ICE_ERR_NOT_SUPPORTED;
+ return ICE_ERR_NOT_SUPPORTED;
}
+}
- return status;
+/**
+ * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
+ * @hw: pointer to the HW struct
+ * @block: the timestamp block to check
+ * @tstamp_ready: storage for the PHY Tx memory status information
+ *
+ * Check the PHY for Tx timestamp memory status. This reports a 64 bit value
+ * which indicates which timestamps in the block may be captured. A set bit
+ * means the timestamp can be read. An unset bit means the timestamp is not
+ * ready and software should avoid reading the register.
+ */
+enum ice_status
+ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E810:
+ return ice_get_phy_tx_tstamp_ready_e810(hw, block,
+ tstamp_ready);
+ case ICE_PHY_E822:
+ return ice_get_phy_tx_tstamp_ready_e822(hw, block,
+ tstamp_ready);
+ break;
+ default:
+ return ICE_ERR_NOT_SUPPORTED;
+ }
}
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index 48a30f1f4e..e25018a68f 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -41,6 +41,14 @@ enum ice_ptp_fec_mode {
ICE_PTP_FEC_MODE_RS_FEC
};
+/* Main timer mode */
+enum ice_src_tmr_mode {
+ ICE_SRC_TMR_MODE_NANOSECONDS,
+ ICE_SRC_TMR_MODE_LOCKED,
+
+ NUM_ICE_SRC_TMR_MODE
+};
+
/**
* struct ice_time_ref_info_e822
* @pll_freq: Frequency of PLL that drives timer ticks in Hz
@@ -123,7 +131,10 @@ extern const struct ice_vernier_info_e822
e822_vernier[NUM_ICE_PTP_LNK_SPD];
/* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
* the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
*/
-#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
+
+#define ICE_E810_PLL_FREQ 812500000
+#define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
+#define E810_OUT_PROP_DELAY_NS 1
/* Device agnostic functions */
u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
@@ -144,9 +155,13 @@ enum ice_status
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
enum ice_status
ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
+void ice_ptp_reset_ts_memory(struct ice_hw *hw);
enum ice_status ice_ptp_init_phc(struct ice_hw *hw);
-
+enum ice_status
+ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
/* E822 family functions */
+#define LOCKED_INCVAL_E822 0x100000000ULL
+
enum ice_status
ice_read_phy_reg_e822(struct ice_hw *hw, u8 port, u16 offset, u32 *val);
enum ice_status
@@ -166,6 +181,7 @@ ice_ptp_read_port_capture_e822(struct ice_hw *hw, u8 port,
enum ice_status
ice_ptp_one_port_cmd_e822(struct ice_hw *hw, u8 port,
enum ice_ptp_tmr_cmd cmd, bool lock_sbq);
+void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);
enum ice_status
ice_cfg_cgu_pll_e822(struct ice_hw *hw, enum ice_time_ref_freq clk_freq,
enum ice_clk_src clk_src);
@@ -236,9 +252,83 @@ enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw,
u8 *data);
enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
bool ice_is_pca9575_present(struct ice_hw *hw);
+/*
+ * ice_is_e830
+ * @hw: pointer to the hardware structure
+ *
+ * returns true if the device is E830 based, false if not.
+ */
+static inline bool ice_is_e830(struct ice_hw *hw)
+{
+ return hw->mac_type == ICE_MAC_E830;
+}
+
void
ice_ptp_process_cgu_err(struct ice_hw *hw, struct ice_rq_event_info *event);
+enum ice_status ice_ptp_init_phy_model(struct ice_hw *hw);
+
+/**
+ * ice_ptp_get_pll_freq - Get PLL frequency
+ * @hw: Board private structure
+ */
+static inline u64
+ice_ptp_get_pll_freq(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E810:
+ return ICE_E810_PLL_FREQ;
+ case ICE_PHY_E822:
+ return ice_e822_pll_freq(ice_e822_time_ref(hw));
+ default:
+ return 0;
+ }
+}
+
+static inline u64
+ice_prop_delay(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E810:
+ return E810_OUT_PROP_DELAY_NS;
+ case ICE_PHY_E822:
+ return ice_e822_pps_delay(ice_e822_time_ref(hw));
+ default:
+ return 0;
+ }
+}
+
+static inline enum ice_time_ref_freq
+ice_time_ref(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E810:
+ case ICE_PHY_E822:
+ return ice_e822_time_ref(hw);
+ default:
+ return ICE_TIME_REF_FREQ_INVALID;
+ }
+}
+
+static inline u64
+ice_get_base_incval(struct ice_hw *hw, enum ice_src_tmr_mode src_tmr_mode)
+{
+ switch (hw->phy_model) {
+
+ case ICE_PHY_E810:
+ return ICE_PTP_NOMINAL_INCVAL_E810;
+ case ICE_PHY_E822:
+ if (src_tmr_mode == ICE_SRC_TMR_MODE_NANOSECONDS &&
+ ice_e822_time_ref(hw) < NUM_ICE_TIME_REF_FREQ)
+ return ice_e822_nominal_incval(ice_e822_time_ref(hw));
+ else
+ return LOCKED_INCVAL_E822;
+
+ break;
+ default:
+ return 0;
+ }
+}
#define PFTSYN_SEM_BYTES 4
diff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h
index 576998549e..d072b0bfe2 100644
--- a/drivers/net/ice/base/ice_type.h
+++ b/drivers/net/ice/base/ice_type.h
@@ -760,7 +760,9 @@ enum ice_time_ref_freq {
ICE_TIME_REF_FREQ_156_250 = 4,
ICE_TIME_REF_FREQ_245_760 = 5,
- NUM_ICE_TIME_REF_FREQ
+ NUM_ICE_TIME_REF_FREQ,
+
+ ICE_TIME_REF_FREQ_INVALID = -1,
};
/* Clock source specification */
@@ -1246,11 +1248,12 @@ struct ice_switch_info {
ice_declare_bitmap(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
};
-/* PHY configuration */
-enum ice_phy_cfg {
- ICE_PHY_E810 = 1,
+/* PHY model */
+enum ice_phy_model {
+ ICE_PHY_UNSUP = -1,
+ ICE_PHY_E810 = 1,
ICE_PHY_E822,
- ICE_PHY_ETH56G,
+ ICE_PHY_E830,
};
/* Port hardware description */
@@ -1277,7 +1280,8 @@ struct ice_hw {
u8 revision_id;
u8 pf_id; /* device profile info */
- enum ice_phy_cfg phy_cfg;
+ enum ice_phy_model phy_model;
+ u8 phy_ports;
u8 logical_pf_id;
u16 max_burst_size; /* driver sets this value */
@@ -1311,7 +1315,6 @@ struct ice_hw {
void *buf, u16 buf_size);
void *aq_send_cmd_param;
u8 dcf_enabled; /* Device Config Function */
-
u8 api_branch; /* API branch version */
u8 api_maj_ver; /* API major version */
u8 api_min_ver; /* API minor version */
@@ -1665,7 +1668,6 @@ struct ice_aq_get_set_rss_lut_params {
/* AQ API version for report default configuration */
#define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
#define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
-
#define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
/* FW version for FEC disable in Auto FEC mode */
diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c
index 6700893bc5..a5bf8317a7 100644
--- a/drivers/net/ice/ice_ethdev.c
+++ b/drivers/net/ice/ice_ethdev.c
@@ -2414,11 +2414,11 @@ ice_dev_init(struct rte_eth_dev *dev)
ice_tm_conf_init(dev);
if (ice_is_e810(hw))
- hw->phy_cfg = ICE_PHY_E810;
+ hw->phy_model = ICE_PHY_E810;
else
- hw->phy_cfg = ICE_PHY_E822;
+ hw->phy_model = ICE_PHY_E822;
- if (hw->phy_cfg == ICE_PHY_E822) {
+ if (hw->phy_model == ICE_PHY_E822) {
ret = ice_start_phy_timer_e822(hw, hw->pf_id, true);
if (ret)
PMD_INIT_LOG(ERR, "Failed to start phy timer\n");
--
2.25.1
