Add a possibility to mark all transmitted/received timestamps as invalid
by clearing PHY OFFSET_READY registers.
Signed-off-by: Karol Kolacinski <karol.kolacin...@intel.com>
Signed-off-by: Qiming Yang <qiming.y...@intel.com>
---
drivers/net/ice/base/ice_adminq_cmd.h | 4 +
drivers/net/ice/base/ice_ptp_hw.c | 126 ++++++++------------------
drivers/net/ice/base/ice_ptp_hw.h | 1 +
3 files changed, 43 insertions(+), 88 deletions(-)
diff --git a/drivers/net/ice/base/ice_adminq_cmd.h
b/drivers/net/ice/base/ice_adminq_cmd.h
index cd4a6ffddf..c51054ecc1 100644
--- a/drivers/net/ice/base/ice_adminq_cmd.h
+++ b/drivers/net/ice/base/ice_adminq_cmd.h
@@ -2897,6 +2897,10 @@ enum ice_aqc_driver_params {
ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR0 = 0,
/* OS clock index for PTP timer Domain 1 */
ICE_AQC_DRIVER_PARAM_CLK_IDX_TMR1,
+ /* Request ID to recalibrate PHC logic */
+ ICE_AQC_DRIVER_PARAM_PHC_RECALC,
+ /* Indicates that PTP clock controller failed */
+ ICE_AQC_DRIVER_PARAM_PTP_CC_FAILED,
/* Add new parameters above */
ICE_AQC_DRIVER_PARAM_MAX = 16,
diff --git a/drivers/net/ice/base/ice_ptp_hw.c
b/drivers/net/ice/base/ice_ptp_hw.c
index a638bb114c..f27131efcc 100644
--- a/drivers/net/ice/base/ice_ptp_hw.c
+++ b/drivers/net/ice/base/ice_ptp_hw.c
@@ -2027,47 +2027,6 @@ enum ice_status ice_phy_cfg_tx_offset_e822(struct ice_hw
*hw, u8 port)
return ICE_SUCCESS;
}
-/**
- * ice_phy_cfg_fixed_tx_offset_e822 - Configure Tx offset for bypass mode
- * @hw: pointer to the HW struct
- * @port: the PHY port to configure
- *
- * Calculate and program the fixed Tx offset, and indicate that the offset is
- * ready. This can be used when operating in bypass mode.
- */
-static enum ice_status
-ice_phy_cfg_fixed_tx_offset_e822(struct ice_hw *hw, u8 port)
-{
- enum ice_ptp_link_spd link_spd;
- enum ice_ptp_fec_mode fec_mode;
- enum ice_status status;
- u64 total_offset;
-
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
-
- total_offset = ice_calc_fixed_tx_offset_e822(hw, link_spd);
-
- /* Program the fixed Tx offset into the P_REG_TOTAL_TX_OFFSET_L
- * register, then indicate that the Tx offset is ready. After this,
- * timestamps will be enabled.
- *
- * Note that this skips including the more precise offsets generated
- * by the Vernier calibration.
- */
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_TX_OFFSET_L,
- total_offset);
- if (status)
- return status;
-
- status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 1);
- if (status)
- return status;
-
- return ICE_SUCCESS;
-}
-
/**
* ice_phy_calc_pmd_adj_e822 - Calculate PMD adjustment for Rx
* @hw: pointer to the HW struct
@@ -2348,43 +2307,33 @@ enum ice_status ice_phy_cfg_rx_offset_e822(struct
ice_hw *hw, u8 port)
return ICE_SUCCESS;
}
+
/**
- * ice_phy_cfg_fixed_rx_offset_e822 - Configure fixed Rx offset for bypass mode
+ * ice_ptp_clear_phy_offset_ready_e822 - Clear PHY TX_/RX_OFFSET_READY
registers
* @hw: pointer to the HW struct
- * @port: the PHY port to configure
*
- * Calculate and program the fixed Rx offset, and indicate that the offset is
- * ready. This can be used when operating in bypass mode.
+ * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
+ * and received timestamps as invalid.
*/
-static enum ice_status
-ice_phy_cfg_fixed_rx_offset_e822(struct ice_hw *hw, u8 port)
+static enum ice_status ice_ptp_clear_phy_offset_ready_e822(struct ice_hw *hw)
{
- enum ice_ptp_link_spd link_spd;
- enum ice_ptp_fec_mode fec_mode;
- enum ice_status status;
- u64 total_offset;
-
- status = ice_phy_get_speed_and_fec_e822(hw, port, &link_spd, &fec_mode);
- if (status)
- return status;
+ u8 port;
- total_offset = ice_calc_fixed_rx_offset_e822(hw, link_spd);
+ for (port = 0; port < hw->phy_ports; port++) {
+ enum ice_status status;
- /* Program the fixed Rx offset into the P_REG_TOTAL_RX_OFFSET_L
- * register, then indicate that the Rx offset is ready. After this,
- * timestamps will be enabled.
- *
- * Note that this skips including the more precise offsets generated
- * by Vernier calibration.
- */
- status = ice_write_64b_phy_reg_e822(hw, port, P_REG_TOTAL_RX_OFFSET_L,
- total_offset);
- if (status)
- return status;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_TX_OR, 0);
+ if (status) {
+ ice_warn(hw, "Failed to clear PHY TX_OFFSET_READY
register\n");
+ return status;
+ }
- status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 1);
- if (status)
- return status;
+ status = ice_write_phy_reg_e822(hw, port, P_REG_RX_OR, 0);
+ if (status) {
+ ice_warn(hw, "Failed to clear PHY RX_OFFSET_READY
register\n");
+ return status;
+ }
+ }
return ICE_SUCCESS;
}
@@ -2666,24 +2615,6 @@ ice_start_phy_timer_e822(struct ice_hw *hw, u8 port,
bool bypass)
if (status)
return status;
- if (bypass) {
- val |= P_REG_PS_BYPASS_MODE_M;
- /* Enter BYPASS mode, enabling timestamps immediately. */
- status = ice_write_phy_reg_e822(hw, port, P_REG_PS, val);
- if (status)
- return status;
-
- /* Program the fixed Tx offset */
- status = ice_phy_cfg_fixed_tx_offset_e822(hw, port);
- if (status)
- return status;
-
- /* Program the fixed Rx offset */
- status = ice_phy_cfg_fixed_rx_offset_e822(hw, port);
- if (status)
- return status;
- }
-
ice_debug(hw, ICE_DBG_PTP, "Enabled clock on PHY port %u\n", port);
return ICE_SUCCESS;
@@ -3841,6 +3772,25 @@ ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64
at_time, s32 adj)
return ice_ptp_tmr_cmd(hw, ICE_PTP_ADJ_TIME_AT_TIME, true);
}
+/**
+ * ice_ptp_clear_phy_offset_ready - Clear PHY TX_/RX_OFFSET_READY registers
+ * @hw: pointer to the HW struct
+ *
+ * Clear PHY TX_/RX_OFFSET_READY registers, effectively marking all transmitted
+ * and received timestamps as invalid.
+ */
+enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw)
+{
+ switch (hw->phy_model) {
+ case ICE_PHY_E810:
+ return ICE_SUCCESS;
+ case ICE_PHY_E822:
+ return ice_ptp_clear_phy_offset_ready_e822(hw);
+ default:
+ return ICE_ERR_NOT_SUPPORTED;
+ }
+}
+
/**
* ice_read_phy_tstamp - Read a PHY timestamp from the timestamp block
* @hw: pointer to the HW struct
diff --git a/drivers/net/ice/base/ice_ptp_hw.h
b/drivers/net/ice/base/ice_ptp_hw.h
index e25018a68f..f4d64ea02b 100644
--- a/drivers/net/ice/base/ice_ptp_hw.h
+++ b/drivers/net/ice/base/ice_ptp_hw.h
@@ -151,6 +151,7 @@ enum ice_status ice_ptp_write_incval_locked(struct ice_hw
*hw, u64 incval,
enum ice_status ice_ptp_adj_clock(struct ice_hw *hw, s32 adj, bool lock_sbq);
enum ice_status
ice_ptp_adj_clock_at_time(struct ice_hw *hw, u64 at_time, s32 adj);
+enum ice_status ice_ptp_clear_phy_offset_ready(struct ice_hw *hw);
enum ice_status
ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
enum ice_status
--
2.25.1
