Hi Nathan, Thanks for the reply. The round-robin interval was set to 200ms and reducing it down to 10 marginally improved the transfer speed. Our current code base and dev board is running a slightly quicker clock than what I used when I measured 75KiB/s, and the current setup is transferring at 100KiB/s with a RR interval of 200 and this increases to 135KiB/s with a RR interval of 10ms.
Yes I do have access to an oscilloscope and logic analyzer so will endeavour to obtain some traces tomorrow to rule in/out possible unexpected delays and/or noise. *Kind regards,* *Radek Pesina* On Wed, 31 May 2023 at 11:33, Nathan Hartman <hartman.nat...@gmail.com> wrote: > On Tue, May 30, 2023 at 8:07 PM Radek Pesina <radek.pes...@motec.com.au> > wrote: > > (snip) > > *Configurations Tested:* > > > > For eMMC, I've tried optimising the menuconfig settings to improve it, > > including options such as below. However, the performance remains > > lacking: > > > > - Turning on CONFIG_MEMCPY_VIK gave slight improvement > > - Setting USEC_PER_TICK to 1000 or below gave most improvement, > however > > at the detriment of other aspects of the system. The fastest speeds > > observed by adjusting this was ~370KiB/s write and 700KiB/s read > though > > overall this was unacceptable given the effect on the rest of the > > system. > > - Adjusting LittleFS parameters (e.g. > > CONFIG_FS_LITTLEFS_PROGRAM_SIZE_FACTOR, > > CONFIG_FS_LITTLEFS_READ_SIZE_FACTOR, > > CONFIG_FS_LITTLEFS_BLOCK_SIZE_FACTOR, > > CONFIG_FS_LITTLEFS_CACHE_SIZE_FACTOR, > CONFIG_FS_LITTLEFS_LOOKAHEAD_SIZE > > - Ensuring SD/eMMC DMA read/writes are enabled. > > - Setting MMCSD_MULTIBLOCK_LIMIT to 0 > > > > (snip) > > Out of curiosity, what is the value of CONFIG_RR_INTERVAL, and, if you > reduce it to something like 20 or 10, does that show any improvement? > > Do you have an oscilloscope or logic analyzer available to monitor the > signals between the microcontroller and MMC? That might shed additional > light on this. E.g., extremely noisy signals, intermittent signals, > unexpectedly long delays between bursts of communication, etc. > > Nathan >
