Reviewed-by: Guo Dong <guo.d...@intel.com>
-----Original Message-----
From: Sean Rhodes <sean@starlabs.systems>
Sent: Wednesday, March 30, 2022 11:29 AM
To: devel@edk2.groups.io
Cc: Tan, Lean Sheng <sheng....@9elements.com>; Dong, Guo <guo.d...@intel.com>;
Ni, Ray <ray...@intel.com>; Ma, Maurice <maurice...@intel.com>; You, Benjamin
<benjamin....@intel.com>; Rhodes, Sean <sean@starlabs.systems>; Patrick Rudolph
<patrick.rudo...@9elements.com>
Subject: [PATCH 1/2] UefiPayloadPkg: Fix PciHostBridgeLib
From: Lean Sheng Tan <sheng....@9elements.com>
Don't assume a 64bit register always holds an address greater than 4GB.
Check the value in the register and decide which Aperature it should be
assigned to.
Fixes assertion
"ASSERT [PciHostBridgeDxe] Bridge->MemAbove4G.Base >= 0x0000000100000000ULL".
Tested with coreboot as bootloader on platforms that have PCI resource above
4GiB and on platforms that don't have resource above 4GiB.
Cc: Guo Dong <guo.d...@intel.com>
Cc: Ray Ni <ray...@intel.com>
Cc: Maurice Ma <maurice...@intel.com>
Cc: Benjamin You <benjamin....@intel.com>
Cc: Sean Rhodes <sean@starlabs.systems>
Signed-off-by: Patrick Rudolph <patrick.rudo...@9elements.com>
---
.../Library/PciHostBridgeLib/PciHostBridgeSupport.c | 13 +++++++++----
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index 8a890b6b53..e1faa24ae7 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -354,14 +354,19 @@ ScanForRootBridges (
Base = ((UINT32)Pci.Bridge.PrefetchableMemoryBase & 0xfff0) << 16;
Limit = (((UINT32)Pci.Bridge.PrefetchableMemoryLimit & 0xfff0)
<< 16) | 0xfffff;- MemAperture = &Mem;+ if (Value
== BIT0) {- Base |= LShiftU64
(Pci.Bridge.PrefetchableBaseUpper32, 32);- Limit |= LShiftU64
(Pci.Bridge.PrefetchableLimitUpper32, 32);- MemAperture =
&MemAbove4G;+ Base |= LShiftU64
(Pci.Bridge.PrefetchableBaseUpper32, 32);+ Limit |= LShiftU64
(Pci.Bridge.PrefetchableLimitUpper32, 32); } if ((Base >
0) && (Base < Limit)) {+ if (Base < BASE_4GB) {+
MemAperture = &Mem;+ } else {+ MemAperture =
&MemAbove4G;+ }+ if (MemAperture->Base > Base) {
MemAperture->Base = Base; }--
2.32.0
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