On Thu, Oct 13, 2022 at 02:10:49PM +0000, Chang, Abner wrote: > [AMD Official Use Only - General] > > > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L > > via groups.io > > Sent: Thursday, October 13, 2022 5:58 PM > > To: devel@edk2.groups.io > > Cc: Michael D Kinney <michael.d.kin...@intel.com>; Liming Gao > > <gaolim...@byosoft.com.cn>; Zhiguang Liu <zhiguang....@intel.com>; Daniel > > Schaefer <g...@danielschaefer.me> > > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 03/34] > > MdePkg/BaseLib: RISC-V: Add few more helper functions > > > > Caution: This message originated from an External Source. Use proper > > caution when opening attachments, clicking links, or responding. > > > > > > REF: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&data=05%7C01%7Ca > > bner.chang%40amd.com%7Cb23d246aae8843c15cd108daad018f1b%7C3dd89 > > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519458082377%7CUnkn > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=Kflz7rvGivG00Ij > > 6thrbhdf%2Bd1hVU7wBxEi45P6Ti0k%3D&reserved=0 > > > > Few of the basic helper functions required for any RISC-V CPU were added in > > edk2-platforms. To support qemu virt, they need to be added in BaseLib. > > > > Cc: Michael D Kinney <michael.d.kin...@intel.com> > > Cc: Liming Gao <gaolim...@byosoft.com.cn> > > Cc: Zhiguang Liu <zhiguang....@intel.com> > > Cc: Daniel Schaefer <g...@danielschaefer.me> > > Signed-off-by: Sunil V L <suni...@ventanamicro.com> > > --- > > MdePkg/Library/BaseLib/BaseLib.inf | 2 + > > MdePkg/Include/Library/BaseLib.h | 50 +++++++++++++++++ > > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S | 31 +++++++++++ > > MdePkg/Library/BaseLib/RiscV64/ReadTimer.S | 24 +++++++++ > > .../Library/BaseLib/RiscV64/RiscVInterrupt.S | 53 +++++++++++++++++-- > > 5 files changed, 156 insertions(+), 4 deletions(-) create mode 100644 > > MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > create mode 100644 MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > > > diff --git a/MdePkg/Library/BaseLib/BaseLib.inf > > b/MdePkg/Library/BaseLib/BaseLib.inf > > index 6be5be9428f2..86d7bb080971 100644 > > --- a/MdePkg/Library/BaseLib/BaseLib.inf > > +++ b/MdePkg/Library/BaseLib/BaseLib.inf > > @@ -401,6 +401,8 @@ [Sources.RISCV64] > > RiscV64/RiscVCpuPause.S | GCC > > RiscV64/RiscVInterrupt.S | GCC > > RiscV64/FlushCache.S | GCC > > + RiscV64/CpuScratch.S | GCC > > + RiscV64/ReadTimer.S | GCC > > > > [Packages] > > MdePkg/MdePkg.dec > > diff --git a/MdePkg/Include/Library/BaseLib.h > > b/MdePkg/Include/Library/BaseLib.h > > index a6f9a194ef1c..9724b84eef89 100644 > > --- a/MdePkg/Include/Library/BaseLib.h > > +++ b/MdePkg/Include/Library/BaseLib.h > > @@ -150,6 +150,56 @@ typedef struct { > > > > #define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8 > > > > +VOID > > + RiscVSetSupervisorScratch ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorScratch ( > > + VOID > > + ); > > + > > +VOID > > + RiscVSetSupervisorStvec ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorStvec ( > > + VOID > > + ); > > + > > +UINT64 > > +RiscVGetSupervisorTrapCause ( > > + VOID > > + ); > > + > > +VOID > > + RiscVSetSupervisorAddressTranslationRegister ( > > + UINT64 > > + ); > > + > > +UINT64 > > +RiscVReadTimer ( > > + VOID > > + ); > > + > > +VOID > > +RiscVEnableTimerInterrupt ( > > + VOID > > + ); > > + > > +VOID > > +RiscVDisableTimerInterrupt ( > > + VOID > > + ); > > + > > +VOID > > +RiscVClearPendingTimerInterrupt ( > > + VOID > > + ); > > + > > #endif // defined (MDE_CPU_RISCV64) > > > > // > > diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > new file mode 100644 > > index 000000000000..dd7adc21eb07 > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/CpuScratch.S > > @@ -0,0 +1,31 @@ > > +//--------------------------------------------------------------------- > > +--------- > > +// > > +// CPU scratch register related functions for RISC-V // // Copyright > > +(c) 2020, Hewlett Packard Enterprise Development LP. All rights > > +reserved.<BR> // // SPDX-License-Identifier: BSD-2-Clause-Patent // > > +//--------------------------------------------------------------------- > > +--------- > > + > > +#include <Register/RiscV64/RiscVImpl.h> > > + > > +.data > > +.align 3 > > +.section .text > > + > > +// > > +// Set Supervisor mode scratch. > > +// @param a0 : Value set to Supervisor mode scratch // ASM_FUNC > > +(RiscVSetSupervisorScratch) > > + csrrw a1, CSR_SSCRATCH, a0 > > + ret > > + > > +// > > +// Get Supervisor mode scratch. > > +// @retval a0 : Value in Supervisor mode scratch // ASM_FUNC > > +(RiscVGetSupervisorScratch) > > + csrr a0, CSR_SSCRATCH > > + ret > > diff --git a/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > > new file mode 100644 > > index 000000000000..bdddb67618ab > > --- /dev/null > > +++ b/MdePkg/Library/BaseLib/RiscV64/ReadTimer.S > Hi Sunil, > Where is this code comes from? Was it written by HPE? If not then you can > remove HPE copyright, otherwise please remove Ventana. > Thanks > Abner Yes, I think I missed some of these files after your recommendation last time. Will remove Ventana. This is existing code in edk2-platforms repo just with different name.
Thanks! Sunil -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95158): https://edk2.groups.io/g/devel/message/95158 Mute This Topic: https://groups.io/mt/94300383/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-