On Thu, Oct 13, 2022 at 12:59:32PM +0000, Chang, Abner wrote: > [AMD Official Use Only - General] > > > > > -----Original Message----- > > From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sunil V L > > via groups.io > > Sent: Thursday, October 13, 2022 5:58 PM > > To: devel@edk2.groups.io > > Cc: Daniel Schaefer <g...@danielschaefer.me>; Michael D Kinney > > <michael.d.kin...@intel.com>; Liming Gao <gaolim...@byosoft.com.cn>; > > Zhiguang Liu <zhiguang....@intel.com> > > Subject: [edk2-devel] [edk2-staging/RiscV64QemuVirt PATCH V3 01/34] > > MdePkg/Register: Add register definition header files for RISC-V > > > > Caution: This message originated from an External Source. Use proper > > caution when opening attachments, clicking links, or responding. > > > > > > REF: > > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fbugz > > illa.tianocore.org%2Fshow_bug.cgi%3Fid%3D4076&data=05%7C01%7Ca > > bner.chang%40amd.com%7C7e426705a0a5494fddb608daad0188ff%7C3dd89 > > 61fe4884e608e11a82d994e183d%7C0%7C0%7C638012519360901317%7CUnkn > > own%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik > > 1haWwiLCJXVCI6Mn0%3D%7C3000%7C%7C%7C&sdata=brw9id8sl20kW > > gKGn0ltbrgPxdRwNZvA2nOCX3CAidU%3D&reserved=0 > > > > Add register definitions and access routines for RISC-V. These headers are > > leveraged from opensbi repo. > > > > Cc: Daniel Schaefer <g...@danielschaefer.me> > > Cc: Michael D Kinney <michael.d.kin...@intel.com> > > Cc: Liming Gao <gaolim...@byosoft.com.cn> > > Cc: Zhiguang Liu <zhiguang....@intel.com> > > Signed-off-by: Sunil V L <suni...@ventanamicro.com> > > --- > > .../Include/Register/RiscV64/RiscVEncoding.h | 125 ++++++++++++++++++ > > MdePkg/Include/Register/RiscV64/RiscVImpl.h | 25 ++++ > > 2 files changed, 150 insertions(+) > > create mode 100644 MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > create mode 100644 MdePkg/Include/Register/RiscV64/RiscVImpl.h > > > > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > new file mode 100644 > > index 000000000000..434436b37fcf > > --- /dev/null > > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > > @@ -0,0 +1,125 @@ > > +/** @file > > + RISC-V CSR encodings > > + > > + Copyright (c) 2019, Western Digital Corporation or its affiliates. > > + All rights reserved.<BR> Copyright (c) 2022, Ventana Micro Systems > > + Inc. All rights reserved.<BR> > > + SPDX-License-Identifier: BSD-2-Clause-Patent > > + > > +**/ > > + > > +#ifndef RISCV_ENCODING_H_ > > +#define RISCV_ENCODING_H_ > > + > > +/* clang-format off */ > > +#define MSTATUS_SIE 0x00000002UL > > +#define MSTATUS_MIE 0x00000008UL > > +#define MSTATUS_SPIE_SHIFT 5 > > +#define MSTATUS_SPIE (1UL << MSTATUS_SPIE_SHIFT) > > +#define MSTATUS_UBE 0x00000040UL > > +#define MSTATUS_MPIE 0x00000080UL > > +#define MSTATUS_SPP_SHIFT 8 > > +#define MSTATUS_SPP (1UL << MSTATUS_SPP_SHIFT) > > +#define MSTATUS_MPP_SHIFT 11 > > +#define MSTATUS_MPP (3UL << MSTATUS_MPP_SHIFT) > > + > > +#define SSTATUS_SIE MSTATUS_SIE > > +#define SSTATUS_SPIE_SHIFT MSTATUS_SPIE_SHIFT > > +#define SSTATUS_SPIE MSTATUS_SPIE > > +#define SSTATUS_SPP_SHIFT MSTATUS_SPP_SHIFT > > +#define SSTATUS_SPP MSTATUS_SPP > > + > > +#define IRQ_S_SOFT 1 > > +#define IRQ_VS_SOFT 2 > > +#define IRQ_M_SOFT 3 > > +#define IRQ_S_TIMER 5 > > +#define IRQ_VS_TIMER 6 > > +#define IRQ_M_TIMER 7 > > +#define IRQ_S_EXT 9 > > +#define IRQ_VS_EXT 10 > > +#define IRQ_M_EXT 11 > > +#define IRQ_S_GEXT 12 > > +#define IRQ_PMU_OVF 13 > > + > > +#define MIP_SSIP (1UL << IRQ_S_SOFT) > > +#define MIP_VSSIP (1UL << IRQ_VS_SOFT) > > +#define MIP_MSIP (1UL << IRQ_M_SOFT) > > +#define MIP_STIP (1UL << IRQ_S_TIMER) > > +#define MIP_VSTIP (1UL << IRQ_VS_TIMER) > > +#define MIP_MTIP (1UL << IRQ_M_TIMER) > > +#define MIP_SEIP (1UL << IRQ_S_EXT) > > +#define MIP_VSEIP (1UL << IRQ_VS_EXT) > > +#define MIP_MEIP (1UL << IRQ_M_EXT) > > +#define MIP_SGEIP (1UL << IRQ_S_GEXT) > > +#define MIP_LCOFIP (1UL << IRQ_PMU_OVF) > > + > > +#define SIP_SSIP MIP_SSIP > > +#define SIP_STIP MIP_STIP > > + > > +#define PRV_U 0UL > > +#define PRV_S 1UL > > +#define PRV_M 3UL > > + > > +#define SATP64_MODE 0xF000000000000000ULL #define SATP64_ASID > > +0x0FFFF00000000000ULL > > +#define SATP64_PPN 0x00000FFFFFFFFFFFULL > > + > > +#define SATP_MODE_OFF 0UL > > +#define SATP_MODE_SV32 1UL > > +#define SATP_MODE_SV39 8UL > > +#define SATP_MODE_SV48 9UL > > +#define SATP_MODE_SV57 10UL > > +#define SATP_MODE_SV64 11UL > > + > > +#define SATP_MODE SATP64_MODE > > + > > +/* ===== User-level CSRs ===== */ > Would you like to have the consistent comment style as /* Supervisor > Configuration */ in below (without the equal signs)? Thus the comments are in > the same style in this file. > You can fix this in the next version.
Sure. Will update the comments. Thanks! > > Not the reviewer or maintainer, however Acked-by: Abner Chang > <abner.ch...@amd.com> > Thanks > Abner -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#95157): https://edk2.groups.io/g/devel/message/95157 Mute This Topic: https://groups.io/mt/94300380/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-