This series adds MMU support for RISC-V. Only SV39/48/57 modes
are supported and tested. The MMU is required to support setting
page attribute which is the first basic step to support security
booting on RISC-V.
There are three parts:
1. Add MMU core to UefiCpuPkg. MMU will be enabled during
CpuDxe initialization.
2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base
address to GCD if already done.
3. Enable MMU for RiscVVirt platform and populating its device
resources in SEC phase. All resources should be populated in HOB
or added to GCD by driver before accessing them when MMU enabled.
Tuan Phan (7):
MdePkg/BaseLib: RISC-V: Support getting satp register value
MdePkg/Register: RISC-V: Add satp mode bits shift definition
UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode
OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size
OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists
OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform
devices
OvmfPkg/RiscVVirt: Enable MMU with SV39 mode
MdePkg/Include/Library/BaseLib.h | 5 +
.../Include/Register/RiscV64/RiscVEncoding.h | 7 +-
MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 +
.../VirtNorFlashStaticLib.c | 3 +-
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 17 -
OvmfPkg/RiscVVirt/Sec/Platform.c | 62 +++
OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 +
OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 10 +-
UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 1 +
UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 5 +
UefiCpuPkg/CpuDxeRiscV64/Mmu.c | 493 ++++++++++++++++++
UefiCpuPkg/CpuDxeRiscV64/Mmu.h | 33 ++
UefiCpuPkg/CpuDxeRiscV64/MmuCore.S | 29 ++
UefiCpuPkg/UefiCpuPkg.dec | 8 +
16 files changed, 676 insertions(+), 32 deletions(-)
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.c
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/Mmu.h
create mode 100644 UefiCpuPkg/CpuDxeRiscV64/MmuCore.S
--
2.25.1
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