As MMU will be enabled in CpuDxe, remove the code that set up satp
mode in SEC phase.
Enable SV39 as default mode.
Signed-off-by: Tuan Phan <tp...@ventanamicro.com>
---
OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 +
OvmfPkg/RiscVVirt/Sec/Memory.c | 17 -----------------
2 files changed, 1 insertion(+), 17 deletions(-)
diff --git a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
index 731f54f73f81..ef268481ca07 100644
--- a/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
+++ b/OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc
@@ -207,6 +207,7 @@
gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength|0
gEfiMdePkgTokenSpaceGuid.PcdSpinLockTimeout|10000000
gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|320
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVSatpMode|8
# DEBUG_ASSERT_ENABLED 0x01
# DEBUG_PRINT_ENABLED 0x02
diff --git a/OvmfPkg/RiscVVirt/Sec/Memory.c b/OvmfPkg/RiscVVirt/Sec/Memory.c
index 70935b07b56b..0b589cd1d071 100644
--- a/OvmfPkg/RiscVVirt/Sec/Memory.c
+++ b/OvmfPkg/RiscVVirt/Sec/Memory.c
@@ -110,21 +110,6 @@ AddMemoryRangeHob (
AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));
}
-/**
- Configure MMU
-**/
-STATIC
-VOID
-InitMmu (
- )
-{
- //
- // Set supervisor translation mode to Bare mode
- //
- RiscVSetSupervisorAddressTranslationRegister ((UINT64)SATP_MODE_OFF << 60);
- DEBUG ((DEBUG_INFO, "%a: Set Supervisor address mode to bare-metal mode.\n",
__FUNCTION__));
-}
-
/**
Publish system RAM and reserve memory regions.
@@ -255,8 +240,6 @@ MemoryPeimInitialization (
}
}
- InitMmu ();
-
BuildMemoryTypeInformationHob ();
return EFI_SUCCESS;
--
2.25.1
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