Looks reasonable to me (but my email view of the patch is corrupted... so please follow up with a link to a Github branch)
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com> > -----Original Message----- > From: Tuan Phan <tp...@ventanamicro.com> > Sent: Friday, April 14, 2023 1:58 PM > To: devel@edk2.groups.io > Cc: Kinney, Michael D <michael.d.kin...@intel.com>; Gao, Liming > <gaolim...@byosoft.com.cn>; Liu, Zhiguang <zhiguang....@intel.com>; > suni...@ventanamicro.com; g...@danielschaefer.me; Warkentin, Andrei > <andrei.warken...@intel.com>; Tuan Phan <tp...@ventanamicro.com> > Subject: [PATCH v2 2/6] MdePkg/Register: RISC-V: Add satp mode bits shift > definition > > The satp mode bits shift is used cross modules. It should be defined in one > place. > > Signed-off-by: Tuan Phan <tp...@ventanamicro.com> > --- > MdePkg/Include/Register/RiscV64/RiscVEncoding.h | 7 ++++--- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > index 5c2989b797bf..2bde8db478ff 100644 > --- a/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > +++ b/MdePkg/Include/Register/RiscV64/RiscVEncoding.h > @@ -58,9 +58,10 @@ > #define PRV_S 1UL #define PRV_M 3UL -#define SATP64_MODE > 0xF000000000000000ULL-#define SATP64_ASID 0x0FFFF00000000000ULL- > #define SATP64_PPN 0x00000FFFFFFFFFFFULL+#define SATP64_MODE > 0xF000000000000000ULL+#define SATP64_MODE_SHIFT 60+#define > SATP64_ASID 0x0FFFF00000000000ULL+#define SATP64_PPN > 0x00000FFFFFFFFFFFULL #define SATP_MODE_OFF 0UL #define > SATP_MODE_SV32 1UL-- > 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#103170): https://edk2.groups.io/g/devel/message/103170 Mute This Topic: https://groups.io/mt/98269075/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
