Apologies for the late review. I added my comments on GH. Aside from a request for more context for https://github.com/tianocore/edk2/commit/b7387dae40cc3a72562c6461d007d20087ab7414#comments, I think this patch set from a functionality standpoint looks good enough to be submitted.
Reviewed-by: Andrei Warkentin <andrei.warken...@intel.com> From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Tuan Phan Sent: Wednesday, April 19, 2023 5:37 PM To: devel@edk2.groups.io; Warkentin, Andrei <andrei.warken...@intel.com> Cc: Kinney, Michael D <michael.d.kin...@intel.com>; Gao, Liming <gaolim...@byosoft.com.cn>; Liu, Zhiguang <zhiguang....@intel.com>; suni...@ventanamicro.com; g...@danielschaefer.me Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Hi Andrei, Here you go: https://github.com/pttuan/edk2/tree/tphan/riscv_mmu Will put the link in the cover letter next round. From: devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> on behalf of Andrei Warkentin <andrei.warken...@intel.com<mailto:andrei.warken...@intel.com>> Date: Tuesday, April 18, 2023 at 9:04 AM To: Tuan Phan <tp...@ventanamicro.com<mailto:tp...@ventanamicro.com>>, devel@edk2.groups.io<mailto:devel@edk2.groups.io> <devel@edk2.groups.io<mailto:devel@edk2.groups.io>> Cc: Kinney, Michael D <michael.d.kin...@intel.com<mailto:michael.d.kin...@intel.com>>, Gao, Liming <gaolim...@byosoft.com.cn<mailto:gaolim...@byosoft.com.cn>>, Liu, Zhiguang <zhiguang....@intel.com<mailto:zhiguang....@intel.com>>, suni...@ventanamicro.com<mailto:suni...@ventanamicro.com> <suni...@ventanamicro.com<mailto:suni...@ventanamicro.com>>, g...@danielschaefer.me<mailto:g...@danielschaefer.me> <g...@danielschaefer.me<mailto:g...@danielschaefer.me>> Subject: Re: [edk2-devel] [PATCH v2 0/6] RISC-V MMU support Hi Tuan, Do you mind sharing the GitHub branch as well? It would help with the review immensely. A > -----Original Message----- > From: Tuan Phan <tp...@ventanamicro.com<mailto:tp...@ventanamicro.com>> > Sent: Friday, April 14, 2023 1:58 PM > To: devel@edk2.groups.io<mailto:devel@edk2.groups.io> > Cc: Kinney, Michael D > <michael.d.kin...@intel.com<mailto:michael.d.kin...@intel.com>>; Gao, Liming > <gaolim...@byosoft.com.cn<mailto:gaolim...@byosoft.com.cn>>; Liu, Zhiguang > <zhiguang....@intel.com<mailto:zhiguang....@intel.com>>; > suni...@ventanamicro.com<mailto:suni...@ventanamicro.com>; > g...@danielschaefer.me<mailto:g...@danielschaefer.me>; Warkentin, Andrei > <andrei.warken...@intel.com<mailto:andrei.warken...@intel.com>>; Tuan Phan > <tp...@ventanamicro.com<mailto:tp...@ventanamicro.com>> > Subject: [PATCH v2 0/6] RISC-V MMU support > > RISC-V: Add MMU support > > This series adds MMU support for RISC-V. Only SV39/48/57 modes are > supported and tested. The MMU is required to support setting page > attribute which is the first basic step to support security booting on RISC-V. > > There are three parts: > 1. Add MMU base library. MMU will be enabled during CpuDxe initialization. > 2. Fix OvmfPkg/VirtNorFlashDxe that failed to add flash base address to GCD > if already done. > 3. Fix all resources should be populated in HOB or added to GCD by driver > before accessing when MMU enabled. > > Changes in v2: > - Move MMU core to a library. > - Setup SATP mode as highest possible that HW supports. > > Tuan Phan (6): > MdePkg/BaseLib: RISC-V: Support getting satp register value > MdePkg/Register: RISC-V: Add satp mode bits shift definition > UefiCpuPkg: RISC-V: Support MMU with SV39/48/57 mode > OvmfPkg/RiscVVirt: VirtNorFlashPlatformLib: Fix wrong flash size > OvmfPkg/VirtNorFlashDxe: Not add memory space if it exists > OvmfPkg/RiscVVirt: SEC: Add IO memory resource hob for platform > devices > > MdePkg/Include/Library/BaseLib.h | 5 + > MdePkg/Include/Library/BaseRiscVMmuLib.h | 39 ++ > .../Include/Register/RiscV64/RiscVEncoding.h | 7 +- > MdePkg/Library/BaseLib/RiscV64/RiscVMmu.S | 8 + > .../Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c | 569 > ++++++++++++++++++ > .../BaseRiscVMmuLib/BaseRiscVMmuLib.inf | 25 + > MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S | 31 + > .../VirtNorFlashStaticLib.c | 3 +- > OvmfPkg/RiscVVirt/RiscVVirt.dsc.inc | 1 + > OvmfPkg/RiscVVirt/Sec/Memory.c | 18 +- > OvmfPkg/RiscVVirt/Sec/Platform.c | 62 ++ > OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + > OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.c | 9 +- > UefiCpuPkg/CpuDxeRiscV64/CpuDxe.h | 2 + > UefiCpuPkg/CpuDxeRiscV64/CpuDxeRiscV64.inf | 2 + > 16 files changed, 776 insertions(+), 31 deletions(-) create mode 100644 > MdePkg/Include/Library/BaseRiscVMmuLib.h > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.c > create mode 100644 > MdePkg/Library/BaseRiscVMmuLib/BaseRiscVMmuLib.inf > create mode 100644 MdePkg/Library/BaseRiscVMmuLib/RiscVMmuCore.S > > -- > 2.25.1 -=-=-=-=-=-=-=-=-=-=-=- Groups.io Links: You receive all messages sent to this group. View/Reply Online (#104282): https://edk2.groups.io/g/devel/message/104282 Mute This Topic: https://groups.io/mt/98269071/21656 Group Owner: devel+ow...@edk2.groups.io Unsubscribe: https://edk2.groups.io/g/devel/unsub [arch...@mail-archive.com] -=-=-=-=-=-=-=-=-=-=-=-
