Hi Prabin,
Thank you for this patch.
Please see my response inline marked [SAMI].
With that fixed,
Reviewed-by: Sami Mujawar <sami.muja...@arm.com>
Regards,
Sami Mujawar
On 4/3/24 18:33, Prabin CA wrote:
The PcdL2CacheSize PCD specifies the size of L2 cache of the CPU.
Use the size specified by this PCD in the PPTT table of the
RD-N2 platform.
The PLAT_L2_CACHE_SIZE build time parameter is used to set the size of
the CPU's L2 cache and this allows changing the value of the L2 cache
size depending the variant of the RD-N2 platform being build. RD-V2
platform is an example of such a variant.
Signed-off-by: Prabin CA<prabin...@arm.com>
---
Platform/ARM/SgiPkg/RdN2/RdN2.dsc | 4 ++++
Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf | 1 +
Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc | 4 +++-
3 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
index 49a317a930e0..634edc2416c4 100644
--- a/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
+++ b/Platform/ARM/SgiPkg/RdN2/RdN2.dsc
@@ -45,6 +45,10 @@ [PcdsFixedAtBuild.common]
gArmPlatformTokenSpaceGuid.PcdCoreCount|1
gArmPlatformTokenSpaceGuid.PcdClusterCount|16
+!ifdef $(PLAT_L2_CACHE_SIZE)
+ gArmSgiTokenSpaceGuid.PcdL2CacheSize|$(PLAT_L2_CACHE_SIZE)
[SAMI] I think there is no need for PLAT_L2_CACHE_SIZE. The pcd can be
set from the build command line using the something like '--pcd
PcdL2CacheSize=0x10000'.
Can you check, please?
Also update the commit message to document that the Pcd can be
configured from the build command line and provide an example.
[/SAMI]
+!endif
+
################################################################################
#
# Components Section - list of all EDK II Modules needed by this Platform
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
index afc38385c051..fb5e6e72c9e8 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2AcpiTables.inf
@@ -64,6 +64,7 @@ [FixedPcd]
gArmSgiTokenSpaceGuid.PcdGtFrame1Gsiv
gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlk0Base
gArmSgiTokenSpaceGuid.PcdIoVirtSocExpBlkUartEnable
+ gArmSgiTokenSpaceGuid.PcdL2CacheSize
gArmSgiTokenSpaceGuid.PcdMaxAddressBitsPerChip
gArmSgiTokenSpaceGuid.PcdOscLpiEnable
gArmSgiTokenSpaceGuid.PcdOscCppcEnable
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
index b8cb04459be2..c37f04582f9c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2/Pptt.aslc
@@ -21,6 +21,8 @@
#include "SgiAcpiHeader.h"
#include "SgiPlatform.h"
+#define L2_CACHE_SIZE FixedPcdGet32 (PcdL2CacheSize)
+
/** Define helper macro for populating processor core information.
@param [in] PackageId Package instance number.
@@ -81,7 +83,7 @@
EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT (
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */
\
0, /* Next level of cache */
\
- SIZE_1MB, /* Size */
\
+ L2_CACHE_SIZE, /* Size */
\
[SAMI] I think you can use FixedPcdGet32 (PcdL2CacheSize) in the above
macro directly.
[/SAMI]
2048, /* Num of sets */
\
8, /* Associativity */
\
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */
\
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