Hi,
Good to see you have your first modifications working :)
How long does it take to do the synthesis?
How much of the FPGA does it take?
If you run into some tricky stuff that you figured out can you document
it? (like for example problems to synthetize the SoC?)
For synthesis have you used ISE GUI? or the build_bitstream.sh shell
script ?
Was the synthesis OK at the first time?
AFAIK Sebastien sometime has to try the synthesis several times to make
it meet timings! Did you experience this kind of problem too?
I think you should fork Sebastien's milkymist github repository into
your github account, and commit/push into your github repo. So that we
can follow your modifications more easily than collecting the patches
from the Mailing List and applying it to our branch if we want to test it.
Which does not mean you should stop posting patches ;)
It would just be nice to have a git repo to track your changes !
PS : try to commit somewhere the last synthesis logs too, it would be
nice to have access to it :)
Thank you !
Cheers,
Yann Sionneau
Le 15/03/11 11:06, Cristian Paul Peñaranda Rojas a écrit :
Before you can add a master device on the wishbone bus, you need make
the CSR 5 Bits if you want to preserve all the already working devices
on the SoC.
I attached a simple/small patch for that, it worked for me.
Next step will be modify the wishbon bus (shared and swiched one)
I'll keep you posted.
Cristian Paul
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