Sebastien Bourdeauducq wrote: > run 2 boards do that too sometimes; on run 3 maybe the reset circuit is > giving yet more trouble because of PVT variations of the parts which > make it non-working on some boards. Just a guess, but if this is the > case, hopefully Werner's gate-based circuit will be better...
By the way, the reset chip may also be not quite optimal: its threshold voltage is nominally 2.63 V, which means a range of 2.577-2.682 V. The NOR's Vcc(min) is 2.7 V. So if 3V3 raises very slowly when powering on, and each time it drops when powering down, there will be a point where the NOR is below its operating voltage, between Vpenlk(max) and Vpenh(min), and with reset not asserted. Not sure if this matters, though. Furthermore, do we know how 1V2 ramps down ? According to http://en.qi-hardware.com/w/images/e/e3/M1rc2_powerOnOff_sequences_manuscript.jpg 3V3 ramps down quite slowly. If 1V2 and/or 2V5 drop faster than 3V3, the NOR may be fully powered (and the reset circuit too) while the FPGA is already under-supplied. Perhaps it would be better to supply the reset chip from 5 V, which is upstream of all the others, and pick a chip with a higher threshold voltage U10.Vin(min) would be 3.3+0.065 V at 100 mA, 3.3+0.65 V at 1A. Ramp-up should be fast enough that the 200 ms reset duration would cover any latency beteen 5V input and regulator output, with about one order of magnitude of headroom. Another useful addition could be a 1k-10k resistor between U9.VPEN and 3V3. This would allow Flash writes to be completely disabled by wiring VPEN to ground, which could help in future bug hunts. - Werner _______________________________________________ http://lists.milkymist.org/listinfo.cgi/devel-milkymist.org IRC: #milkymist@Freenode Twitter: www.twitter.com/milkymistvj Ideas? http://milkymist.uservoice.com
