On 02/17/2013 05:57 PM, Sébastien Bourdeauducq wrote:
--- a/migen/fhdl/tools.py
+++ b/migen/fhdl/tools.py
@@ -136,7 +136,7 @@ def is_variable(node):
def insert_reset(rst, sl):
targets = list_targets(sl)
- resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x:
x.huid)]
+ resetcode = [t.eq(t.reset) for t in sorted(targets, key=lambda x:
x.huid) if t.reset != None]
return If(rst, *resetcode).Else(*sl)
OK, will apply.
Hmm, actually no - the reset would still act as active-low clock enable
for those signals with reset=None, which I don't like.
I see two solutions:
1) extract the statements that assign to reset=None signals from the
list, and put them after the If(rst, ...).
This is a bit complex considering that you have to take into account
assignments inside conditional statements etc.
2) support "reset-less" clock domains and let the user put assignments
to signals that should not have a reset into such a domain.
Considering that reset-less signals are usually rare (so the complexity
of #1 is less justified), and that clock domains with flexible reset
options are also useful for other purposes (such as a design that only
uses the bitstream load reset values for initializing the FFs) I'm in
favor of #2.
Sébastien
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