On 02/17/2013 09:30 PM, Florent Kermarrec wrote:
In fact the issue I had was in the ASMICON/bankmachine.py l45: self.tag =
Signal(max=self.nslots), with self.nslots=1.
I will have a look at the generated code to see what is generated with migen.
Hmm, indeed, ASMI isn't really meant to be used with a single slot...
It would be much better to implement a Fragment transform function
that breaks down any memory that uses we_granularity into smaller
memories that are we_granularity bits wide each. This way, the
problem would be solved for all memories, not only the Wishbone SRAM.
I think it won't be exactly the same. I have the issue only with the
Cyclone 2, the Cyclone IV is Ok. On the cyclone 2, the M4K does not
support byte enable if read is done continuously. My modification was
only a quick work-around for that. With your solution I will use 4x more
M4K and it will probably won't feet in my fpga.
M4K memory blocks can be configured as 512x8
[http://www.altera.com/literature/hb/cyc2/cyc2_cii51008.pdf].
With the "one memory per byte" solution, the SRAM granularity is four
M4K blocks in 512x8 configuration, i.e. the SRAM size has to be a
multiple of 2KB. This doesn't sound like a difficult constraint.
Sébastien
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