Hi,
thanks for the files, I have merged them. Here are comments and things I
changed:
* use Unix end-of-line characters (eg run dos2unix on the files after
editing them on a Windows machine)
* renamed "rst_level" to "rst_invert" and made it boolean to be
consistent with migen.fhdl.specials.Instance.{ClockPort, ResetPort}
* new-style Module API does not require you to form lists except for
spanning multiple lines (this requirement only comes from the Python
parser) so:
self.comb +=[self.cd.rst.eq(~rst_n)]
can be rewritten as
self.comb += self.cd.rst.eq(~rst_n)
* platform.request returns a new object if you don't specify one.
Additionally, its second parameter defaults to None. So instead of writing:
rst_n = Signal()
platform.request(rst_name, None, rst_n)
you can write:
rst_n = platform.request(rst_name)
* removed unneeded Decimal, struct, Instance, SynthesisDirective,
migen.fhdl.structure, migen.genlib.cdc and CRG imports from altera_quartus
* added reset inversion support to the Xilinx platform as well
* renamed led to user_led to be consistent with other platforms
* fixed minor indentation and style problems in de0nano
* can you send me headers to add to altera_quartus.py and de0nano.py
that state that you are the main author of those files, and with
copyright and license info?
Thanks,
Sebastien
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