--
Robert Jordens.
From 452e299b4ce6b0d959e8353f0560e41a628f14fa Mon Sep 17 00:00:00 2001
From: Robert Jordens <[email protected]>
Date: Fri, 6 Dec 2013 00:51:03 -0700
Subject: [PATCH 1/2] mibuild/xilinx_ise: add support for custom tools and
options
---
mibuild/platforms/lx9_microboard.py | 4 ++++
mibuild/platforms/usrp_b100.py | 4 ++++
mibuild/xilinx_ise.py | 38 ++++++++++++++++++++++---------------
3 files changed, 31 insertions(+), 15 deletions(-)
diff --git a/mibuild/platforms/lx9_microboard.py b/mibuild/platforms/lx9_microboard.py
index c3195e0..84ee5ae 100644
--- a/mibuild/platforms/lx9_microboard.py
+++ b/mibuild/platforms/lx9_microboard.py
@@ -102,6 +102,10 @@ _io = [
class Platform(XilinxISEPlatform):
+ bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g SPI_buswidth:4"
+ ise_commands = """
+promgen -w -spi -c FF -p mcs -o {build_name}.mcs -u 0 {build_name}.bit
+"""
def __init__(self):
XilinxISEPlatform.__init__(self, "xc6slx9-2csg324", _io,
lambda p: CRG_SE(p, "clk_y3", "user_btn"))
diff --git a/mibuild/platforms/usrp_b100.py b/mibuild/platforms/usrp_b100.py
index dc040c4..add6a5b 100644
--- a/mibuild/platforms/usrp_b100.py
+++ b/mibuild/platforms/usrp_b100.py
@@ -113,6 +113,10 @@ _io = [
class Platform(XilinxISEPlatform):
+ xst_opt = """-ifmt MIXED
+-opt_mode SPEED
+-register_balancing yes"""
+ bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes -g UnusedPin:PullUp"
def __init__(self):
XilinxISEPlatform.__init__(self, "xc3s1400a-ft256-4", _io,
lambda p: CRG_DS(p, "clk64", "reset_n", rst_invert=True))
diff --git a/mibuild/xilinx_ise.py b/mibuild/xilinx_ise.py
index 47ee23b..bf5da73 100644
--- a/mibuild/xilinx_ise.py
+++ b/mibuild/xilinx_ise.py
@@ -70,21 +70,18 @@ def _build_ucf(named_sc, named_pc):
r += "\n" + "\n\n".join(named_pc)
return r
-def _build_xst_files(device, sources, build_name):
+def _build_xst_files(device, sources, build_name, xst_opt):
prj_contents = ""
for filename, language in sources:
prj_contents += language + " work " + filename + "\n"
tools.write_to_file(build_name + ".prj", prj_contents)
xst_contents = """run
--ifn %s.prj
+-ifn {build_name}.prj
-top top
--ifmt MIXED
--opt_mode SPEED
--reduce_control_sets auto
--register_balancing yes
--ofn %s.ngc
--p %s""" % (build_name, build_name, device)
+{xst_opt}
+-ofn {build_name}.ngc
+-p {device}""".format(build_name=build_name, xst_opt=xst_opt, device=device)
tools.write_to_file(build_name + ".xst", xst_contents)
def _run_yosys(device, sources, build_name):
@@ -121,7 +118,8 @@ def _is_valid_version(path, v):
except:
return False
-def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt):
+def _run_ise(build_name, ise_path, source, mode, ngdbuild_opt,
+ bitgen_opt, ise_commands):
if sys.platform == "win32" or sys.platform == "cygwin":
source = False
build_script_contents = "# Autogenerated by mibuild\nset -e\n"
@@ -146,9 +144,11 @@ ngdbuild -uc {build_name}.ucf {build_name}.ngc {build_name}.ngd"""
build_script_contents += """
map -ol high -w -o {build_name}_map.ncd {build_name}.ngd {build_name}.pcf
par -ol high -w {build_name}_map.ncd {build_name}.ncd {build_name}.pcf
-bitgen -g LCK_cycle:6 -g Binary:Yes -w {build_name}.ncd {build_name}.bit
+bitgen {bitgen_opt} -w {build_name}.ncd {build_name}.bit
"""
- build_script_contents = build_script_contents.format(build_name=build_name, ngdbuild_opt=ngdbuild_opt)
+ build_script_contents = build_script_contents.format(build_name=build_name,
+ ngdbuild_opt=ngdbuild_opt, bitgen_opt=bitgen_opt)
+ build_script_contents += ise_commands.format(build_name=build_name)
build_script_file = "build_" + build_name + ".sh"
tools.write_to_file(build_script_file, build_script_contents)
@@ -177,6 +177,13 @@ class XilinxMultiReg:
return XilinxMultiRegImpl(dr.i, dr.o, dr.odomain, dr.n)
class XilinxISEPlatform(GenericPlatform):
+ xst_opt = """-ifmt MIXED
+-opt_mode SPEED
+-reduce_control_sets auto
+-register_balancing yes"""
+ ngdbuild_opt = ""
+ bitgen_opt = "-g LCK_cycle:6 -g Binary:Yes"
+ ise_commands = ""
def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = {
NoRetiming: XilinxNoRetiming,
@@ -197,7 +204,7 @@ class XilinxISEPlatform(GenericPlatform):
fragment = fragment.get_fragment()
self.finalize(fragment)
- ngdbuild_opt = ""
+ ngdbuild_opt = self.ngdbuild_opt
if mode == "xst" or mode == "yosys":
v_src, named_sc, named_pc = self.get_verilog(fragment)
@@ -205,12 +212,12 @@ class XilinxISEPlatform(GenericPlatform):
tools.write_to_file(v_file, v_src)
sources = self.sources + [(v_file, "verilog")]
if mode == "xst":
- _build_xst_files(self.device, sources, build_name)
+ _build_xst_files(self.device, sources, build_name, self.xst_opt)
isemode = "xst"
else:
_run_yosys(self.device, sources, build_name)
isemode = "edif"
- ngdbuild_opt = "-p " + self.device
+ ngdbuild_opt += "-p " + self.device
if mode == "mist":
from mist import synthesize
@@ -224,6 +231,7 @@ class XilinxISEPlatform(GenericPlatform):
tools.write_to_file(build_name + ".ucf", _build_ucf(named_sc, named_pc))
if run:
- _run_ise(build_name, ise_path, source, isemode, ngdbuild_opt)
+ _run_ise(build_name, ise_path, source, isemode,
+ ngdbuild_opt, self.bitgen_opt, self.ise_commands)
os.chdir("..")
--
1.8.3.2
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