Le 17/12/13 12:35, Toru Nishimura a écrit :
Here is my imarginal LM32 TLB refill handler in psedo
assember code. I never step across TLB off/on issue here.
It's O(1) algorithm to update TLB content made possible
by layouting PTE in a single linear array in kernel address
space. Note that some i386 OS employs the very same
O(1) lookup strategy but most users are not aware of the fact.
TLBrefill: # sometimes called fast TLB miss handler entry
rcsr $et, CONTEXT
ld $et, 0($et)
wcsr TLBLO, $et
This is also the kind of thing I had in mind for the TLB miss handler
except maybe I would use directories in order to have much smaller page
tables
And then I don't think I would use a CSR for the address of the page
table because CSR is a rare resource :)
I will probably store a pointer to the "current page table" in a well
known location in physical memory.
Except those, indeed I would do something like that :)
Which looks like MIPS fast tlb miss I saw in the really good book "see
MIPS Run" (Linux edition)
Note that it does not check the validity of $et value before TLB
injection before wcsr. The occasion will be catched by another
exceptional condition to be solved by OS (in longer code path)
The O(1) array is mapped in kernel address space by TLB.
There is such an occasion that the ld insn triggers TLB miss
*while exception handler path* and it's the case while EXL bit
takes effect.
-nisimura
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