There are no known ARMv7-M chips with a dual lockstep mode.
Update #3773.
---
bsps/arm/shared/start/start.S | 13 +------------
1 file changed, 1 insertion(+), 12 deletions(-)
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index 80b7d44dbe..a7fd7eda62 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -369,12 +369,7 @@ bsp_start_vector_table_end:
_start:
-#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
- bl bsp_start_init_registers_core
-#endif
-
-#ifdef ARM_MULTILIB_VFP
-#ifdef ARM_MULTILIB_HAS_CPACR
+#if defined(ARM_MULTILIB_VFP) && defined(ARM_MULTILIB_HAS_CPACR)
/*
* Enable CP10 and CP11 coprocessors for privileged and user mode in
* CPACR (bits 20-23). Ensure that write to register completes.
@@ -387,12 +382,6 @@ _start:
isb
#endif
-#ifdef BSP_START_NEEDS_REGISTER_INITIALIZATION
- bl bsp_start_init_registers_vfp
-#endif
-
-#endif /* ARM_MULTILIB_VFP */
-
ldr sp, =_ISR_Stack_area_end
ldr lr, =.Lstart_hook_0_done + 1
b bsp_start_hook_0
--
2.16.4
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