This looks generally ok but is all this visible to any application that includes bsp.h?
It might all need to be moved into a separate header to avoid contaminating everyone's namespace. On Thu, Jul 21, 2022, 10:56 AM Noor Aman <nooraman5...@gmail.com> wrote: > A brief gist of what i found compatible with the older code > ---COMPATIBLE HEADER--- > - BCM2835 timer > - GPIO > - AUX > - GPU timer > ---DIDNT CHECK--- > - SPI > - I2C > ---MINOR CHNAGE--- > - IRQ > - FIQ > ---NOT SURE ABOUT--- > - Watchdog > - Power management > - Mailbox register > > I didnt get any info about power management or watchdog or mailboxes. (It > isnt in the BCM2835 Documention too I think??) > > And to answer your question Alan about if the Aarch64 would require a DTB > or not which you asked me quite earlier. I can say now, you dont, because > every address is defined here already so no need for the DTB. > > > > diff --git a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h > b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h > index eeb48c42f1..a4ed2a01d1 100644 > --- a/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h > +++ b/bsps/aarch64/raspberrypi/include/bsp/raspberrypi.h > @@ -52,15 +52,23 @@ > * @{ > */ > > -#if (BSP_IS_RPI2 == 1) > - #define RPI_PERIPHERAL_BASE 0x3F000000 > +#if (RPI_BSP == RPI2) > + #define RPI_PERIPHERAL_BASE 0X3F000000 > #define BASE_OFFSET 0X3F000000 > + > +#elif (RPI_BSP == RPI4) > + #define RPI_PERIPHERAL_BASE 0xFE000000 > + #define BASE_OFFSET 0xFE000000 > + #define RPI_PERIPHERAL_SIZE 0x01800000 > + > #else > #define RPI_PERIPHERAL_BASE 0x20000000 > #define BASE_OFFSET 0X5E000000 > + > #endif > > -#define RPI_PERIPHERAL_SIZE 0x01000000 > +#ifndef RPI_PERIPHERAL_SIZE > +#define RPI_PERIPHERAL_SIZE 0x01000000 > > /** > * @name Bus to Physical address translation > @@ -543,6 +551,188 @@ > #define BCM2836_IRQ_SOURCE_PMU 0x00000200 > #define BCM2836_IRQ_SOURCE_LOCAL_TIMER 0x00000800 > > + > + > +/** > + * @name Raspberry Pi 4 ARM_LOCAL registers > + * > + * @{ > + */ > + > +#define BCM2711_LOCAL_REGS_BASE 0x4C0000000 > + > +#define BCM2711_LOCAL_ARM_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x00) > +#define BCM2711_LOCAL_CORE_IRQ_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x0c) > +#define BCM2711_LOCAL_PMU_CONTROL_SET (BCM2711_LOCAL_REGS_BASE + 0x10) > +#define BCM2711_LOCAL_PMU_CONTROL_CLR (BCM2711_LOCAL_REGS_BASE + 0x14) > +#define BCM2711_LOCAL_PERI_IRQ_ROUTE0 (BCM2711_LOCAL_REGS_BASE + 0x24) > +#define BCM2711_LOCAL_AXI_QUIET_TIME (BCM2711_LOCAL_REGS_BASE + 0x30) > +#define BCM2711_LOCAL_LOCAL_TIMER_CONTROL (BCM2711_LOCAL_REGS_BASE + 0x34) > +#define BCM2711_LOCAL_LOCAL_TIMER_IRQ (BCM2711_LOCAL_REGS_BASE + > 0x38) > + > +#define BCM2711_LOCAL_TIMER_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x40) > +#define BCM2711_LOCAL_TIMER_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x44) > +#define BCM2711_LOCAL_TIMER_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x48) > +#define BCM2711_LOCAL_TIMER_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x4c) > + > +#define BCM2711_LOCAL_MAILBOX_CNTRL0 (BCM2711_LOCAL_REGS_BASE + 0x50) > +#define BCM2711_LOCAL_MAILBOX_CNTRL1 (BCM2711_LOCAL_REGS_BASE + 0x54) > +#define BCM2711_LOCAL_MAILBOX_CNTRL2 (BCM2711_LOCAL_REGS_BASE + 0x58) > +#define BCM2711_LOCAL_MAILBOX_CNTRL3 (BCM2711_LOCAL_REGS_BASE + 0x5c) > + > +#define BCM2711_LOCAL_IRQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x60) > +#define BCM2711_LOCAL_IRQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x64) > +#define BCM2711_LOCAL_IRQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x68) > +#define BCM2711_LOCAL_IRQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x6c) > + > +#define BCM2711_LOCAL_FIQ_SOURCE0 (BCM2711_LOCAL_REGS_BASE + 0x70) > +#define BCM2711_LOCAL_FIQ_SOURCE1 (BCM2711_LOCAL_REGS_BASE + 0x74) > +#define BCM2711_LOCAL_FIQ_SOURCE2 (BCM2711_LOCAL_REGS_BASE + 0x78) > +#define BCM2711_LOCAL_FIQ_SOURCE3 (BCM2711_LOCAL_REGS_BASE + 0x7c) > + > + > +/** > + * @name Raspberry Pi 4 ARM_C FIQ and IRQ registers > + * > + * @{ > + */ > + > +#define BCM2711_ARMC_REGS_BASE (RPI_PERIPHERAL_BASE + 0xB200) > + > +#define BCM2711_ARMC_IRQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x00) > +#define BCM2711_ARMC_IRQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x04) > +#define BCM2711_ARMC_IRQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x08) > +#define BCM2711_ARMC_IRQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x10) > +#define BCM2711_ARMC_IRQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x14) > +#define BCM2711_ARMC_IRQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x18) > +#define BCM2711_ARMC_IRQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x20) > +#define BCM2711_ARMC_IRQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x24) > +#define BCM2711_ARMC_IRQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x28) > + > +#define BCM2711_ARMC_IRQ_STATUS0 (BCM2711_ARMC_REGS_BASE + 0x30) > +#define BCM2711_ARMC_IRQ_STATUS1 (BCM2711_ARMC_REGS_BASE + 0x34) > +#define BCM2711_ARMC_IRQ_STATUS2 (BCM2711_ARMC_REGS_BASE + 0x38) > + > +#define BCM2711_ARMC_IRQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x40) > +#define BCM2711_ARMC_IRQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x44) > +#define BCM2711_ARMC_IRQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x48) > +#define BCM2711_ARMC_IRQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x50) > +#define BCM2711_ARMC_IRQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x54) > +#define BCM2711_ARMC_IRQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x58) > +#define BCM2711_ARMC_IRQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x60) > +#define BCM2711_ARMC_IRQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x64) > +#define BCM2711_ARMC_IRQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x68) > + > +#define BCM2711_ARMC_IRQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x80) > +#define BCM2711_ARMC_IRQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x84) > +#define BCM2711_ARMC_IRQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x88) > +#define BCM2711_ARMC_IRQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x90) > +#define BCM2711_ARMC_IRQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x94) > +#define BCM2711_ARMC_IRQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x98) > +#define BCM2711_ARMC_IRQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xA0) > +#define BCM2711_ARMC_IRQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xA4) > +#define BCM2711_ARMC_IRQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xA8) > + > +#define BCM2711_ARMC_IRQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0xC0) > +#define BCM2711_ARMC_IRQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0xC4) > +#define BCM2711_ARMC_IRQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0xC8) > +#define BCM2711_ARMC_IRQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0xD0) > +#define BCM2711_ARMC_IRQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0xD4) > +#define BCM2711_ARMC_IRQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0xD8) > +#define BCM2711_ARMC_IRQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0xE0) > +#define BCM2711_ARMC_IRQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0xE4) > +#define BCM2711_ARMC_IRQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0xE8) > + > + > + > +#define BCM2711_ARMC_FIQ0_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x100) > +#define BCM2711_ARMC_FIQ0_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x104) > +#define BCM2711_ARMC_FIQ0_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x108) > +#define BCM2711_ARMC_FIQ0_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x110) > +#define BCM2711_ARMC_FIQ0_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x114) > +#define BCM2711_ARMC_FIQ0_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x118) > +#define BCM2711_ARMC_FIQ0_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x120) > +#define BCM2711_ARMC_FIQ0_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x124) > +#define BCM2711_ARMC_FIQ0_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x128) > + > +#define BCM2711_ARMC_FIQ1_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x140) > +#define BCM2711_ARMC_FIQ1_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x144) > +#define BCM2711_ARMC_FIQ1_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x148) > +#define BCM2711_ARMC_FIQ1_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x150) > +#define BCM2711_ARMC_FIQ1_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x154) > +#define BCM2711_ARMC_FIQ1_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x158) > +#define BCM2711_ARMC_FIQ1_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x160) > +#define BCM2711_ARMC_FIQ1_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x164) > +#define BCM2711_ARMC_FIQ1_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x168) > + > +#define BCM2711_ARMC_FIQ2_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x180) > +#define BCM2711_ARMC_FIQ2_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x184) > +#define BCM2711_ARMC_FIQ2_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x188) > +#define BCM2711_ARMC_FIQ2_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x190) > +#define BCM2711_ARMC_FIQ2_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x194) > +#define BCM2711_ARMC_FIQ2_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x198) > +#define BCM2711_ARMC_FIQ2_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1A0) > +#define BCM2711_ARMC_FIQ2_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1A4) > +#define BCM2711_ARMC_FIQ2_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1A8) > + > +#define BCM2711_ARMC_FIQ3_PENDING0 (BCM2711_ARMC_REGS_BASE + 0x1C0) > +#define BCM2711_ARMC_FIQ3_PENDING1 (BCM2711_ARMC_REGS_BASE + 0x1C4) > +#define BCM2711_ARMC_FIQ3_PENDING2 (BCM2711_ARMC_REGS_BASE + 0x1C8) > +#define BCM2711_ARMC_FIQ3_SET_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1D0) > +#define BCM2711_ARMC_FIQ3_SET_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1D4) > +#define BCM2711_ARMC_FIQ3_SET_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1D8) > +#define BCM2711_ARMC_FIQ3_CLR_EN_0 (BCM2711_ARMC_REGS_BASE + 0x1E0) > +#define BCM2711_ARMC_FIQ3_CLR_EN_1 (BCM2711_ARMC_REGS_BASE + 0x1E4) > +#define BCM2711_ARMC_FIQ3_CLR_EN_2 (BCM2711_ARMC_REGS_BASE + 0x1E8) > + > +#define BCM2711_ARMC_SWIRQ_SET (BCM2711_ARMC_REGS_BASE + 0x1F0) > +#define BCM2711_ARMC_SWIRQ_CLEAR (BCM2711_ARMC_REGS_BASE + 0x1F4) > + > + > +/** > + * @name Raspberry Pi 4 Mailbox registers > + * > + * @{ > + */ > + > + > + > +#define BCM2711_MAILBOX_00_WRITE_SET_BASE 0x4C000080 > +#define BCM2711_MAILBOX_01_WRITE_SET_BASE 0x4C000084 > +#define BCM2711_MAILBOX_02_WRITE_SET_BASE 0x4C000088 > +#define BCM2711_MAILBOX_03_WRITE_SET_BASE 0x4C00008C > +#define BCM2711_MAILBOX_04_WRITE_SET_BASE 0x4C000090 > +#define BCM2711_MAILBOX_05_WRITE_SET_BASE 0x4C000094 > +#define BCM2711_MAILBOX_06_WRITE_SET_BASE 0x4C000098 > +#define BCM2711_MAILBOX_07_WRITE_SET_BASE 0x4C00009C > +#define BCM2711_MAILBOX_08_WRITE_SET_BASE 0x4C0000A0 > +#define BCM2711_MAILBOX_09_WRITE_SET_BASE 0x4C0000A4 > +#define BCM2711_MAILBOX_10_WRITE_SET_BASE 0x4C0000A8 > +#define BCM2711_MAILBOX_11_WRITE_SET_BASE 0x4C0000AC > +#define BCM2711_MAILBOX_12_WRITE_SET_BASE 0x4C0000B0 > +#define BCM2711_MAILBOX_13_WRITE_SET_BASE 0x4C0000B4 > +#define BCM2711_MAILBOX_14_WRITE_SET_BASE 0x4C0000B8 > +#define BCM2711_MAILBOX_15_WRITE_SET_BASE 0x4C0000BC > + > +#define BCM2711_MAILBOX_00_READ_CLEAR_BASE 0x4C0000C0 > +#define BCM2711_MAILBOX_01_READ_CLEAR_BASE 0x4C0000C4 > +#define BCM2711_MAILBOX_02_READ_CLEAR_BASE 0x4C0000C8 > +#define BCM2711_MAILBOX_03_READ_CLEAR_BASE 0x4C0000CC > +#define BCM2711_MAILBOX_04_READ_CLEAR_BASE 0x4C0000D0 > +#define BCM2711_MAILBOX_05_READ_CLEAR_BASE 0x4C0000D4 > +#define BCM2711_MAILBOX_06_READ_CLEAR_BASE 0x4C0000D8 > +#define BCM2711_MAILBOX_07_READ_CLEAR_BASE 0x4C0000DC > +#define BCM2711_MAILBOX_08_READ_CLEAR_BASE 0x4C0000E0 > +#define BCM2711_MAILBOX_09_READ_CLEAR_BASE 0x4C0000E4 > +#define BCM2711_MAILBOX_10_READ_CLEAR_BASE 0x4C0000E8 > +#define BCM2711_MAILBOX_11_READ_CLEAR_BASE 0x4C0000EC > +#define BCM2711_MAILBOX_12_READ_CLEAR_BASE 0x4C0000F0 > +#define BCM2711_MAILBOX_13_READ_CLEAR_BASE 0x4C0000F4 > +#define BCM2711_MAILBOX_14_READ_CLEAR_BASE 0x4C0000F8 > +#define BCM2711_MAILBOX_15_READ_CLEAR_BASE 0x4C0000FC > + > + > + > /** @} */ > > #endif /* LIBBSP_ARM_RASPBERRYPI_RASPBERRYPI_H */ > _______________________________________________ > devel mailing list > devel@rtems.org > http://lists.rtems.org/mailman/listinfo/devel
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