On 30/3/2023 6:22 am, Alex White wrote: > From: "Maldonado, Sergio E. (GSFC-580.0)" <serg > .../microblaze/microblaze_fpga/optuartirq.yml | 20 ++ > .../microblaze/microblaze_fpga/optuseuart.yml | 17 ++ > .../microblaze_fpga/optuseuart1.yml | 17 ++ > .../microblaze_fpga/optuseuart2.yml | 17 ++ > .../microblaze_fpga/optuseuart3.yml | 17 ++ > .../microblaze_fpga/optuseuart4.yml | 17 ++
Are these 4 UARTs dependent on the IP built into the FPGA with the Microblaze core? Chris _______________________________________________ devel mailing list devel@rtems.org http://lists.rtems.org/mailman/listinfo/devel
