Nathan Hand wrote:
Why not

        slice 1) send 1 megabyte
        ...
        slice 2) fifo not drained, reduce fifo to 512kB, wait
        ...
        slice 3) fifo not drained, reduce fifo to 256kB, wait
        ...
        slice 4) fifo drained, send 256kB
        ...
        slice 5) fifo drained, send 256kB


Does the hardware have a register containing a pointer to the current command being executed?

I "solved" a similar problem in the SiS driver by doing it the following way:

1) Push data into the FIFO until it's filled up to a quarter of its size
2) Before pushing further data, wait for the current command pointer to be outside the second quarter (which I am about to write to)
3) Likewise with the third and fourth quarter: Just wait until the current command pointer is outside these, and the write to this quarter without any waiting.


This minimizes CPU waiting to 1/4 of the original extent. Benchmarks have shown that dividing the queue size in smaller parts than quarters makes it slower because of the more frequent polling of the command ptr.

Thomas

--
Thomas Winischhofer
Vienna/Austria
thomas AT winischhofer DOT net          *** http://www.winischhofer.net/
twini AT xfree86 DOT org



_______________________________________________
Devel mailing list
[EMAIL PROTECTED]
http://XFree86.Org/mailman/listinfo/devel

Reply via email to