Hi Marc,
On 03/05/2015 03:05 PM, Marc Zyngier wrote:
> Hi Michal,
>
> On 05/03/15 13:53, Michal Simek wrote:
>> Initial version of device tree for Xilinx ZynqMP SoC.
>>
>> Signed-off-by: Michal Simek <michal.si...@xilinx.com>
>> Acked-by: Sören Brinkmann <soren.brinkm...@xilinx.com>
>> ---
>>
>> Changes in v2:
>> - move timer out of amba_apu bus because it is not on bus
>> Reported by Mark
>> - FIC GICC and GICV addresses - Reported by Rob
>> - Fix copyright
>> - Enable cadence IP in defconfig
>> - Add support for macb multiqueue
>>
>> arch/arm64/Kconfig | 5 +
>> arch/arm64/boot/dts/Makefile | 1 +
>> arch/arm64/boot/dts/xilinx/Makefile | 5 +
>> arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts | 47 +++++
>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 303
>> ++++++++++++++++++++++++++++
>> arch/arm64/configs/defconfig | 3 +
>> 6 files changed, 364 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/xilinx/Makefile
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp.dtsi
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>> new file mode 100644
>> index 000000000000..0a3f40ecd06d
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ep108.dts
>
> [...]
>
>> + gic: interrupt-controller@f9010000 {
>> + compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
>> + #interrupt-cells = <3>;
>> + reg = <0x0 0xf9010000 0x10000>,
>> + <0x0 0xf902f000 0x2000>,
>> + <0x0 0xf9040000 0x20000>,
>> + <0x0 0xf906f000 0x2000>;
>> + interrupt-controller;
>
> Please add the missing GIC maintenance interrupt.Ok. Will add interrupts = <1 9 0xf04>; Thanks, Michal -- Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91 w: www.monstr.eu p: +42-0-721842854 Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/ Maintainer of Linux kernel - Xilinx Zynq ARM architecture Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
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