Don wrote:
Andrei Alexandrescu wrote:
Consider:
struct A {
char a;
align(1) int b;
}
Accesses to b will be rather slow because it's a misaligned read. My
question is, how exactly is that handled on various processors? I seem
to recall various anecdotes (including that misaligned reads on Intel
cause a trap that does the needed double reading, shifting, and
masking), but Google search has surprisingly little on the matter.
Not on Intel. IIRC the trapping happens on Sparc. Misalignment on x86
doesn't hurt much at all, except for doubles and reals.
For the case you mention there'll probably be no misalignment penalty at
all, the latency gets hidden in the early stages of the pipeline.
Although there may be a penalty if you cross a cache line boundary.
Thanks! Are there some online docs that discuss that in detail?
Andrei
