On Tuesday, 18 August 2015 at 23:32:38 UTC, rsw0x wrote:
I believe they're referring to x86 decoding CISC to RISC micro-ops behind the scenes.
Well, not RISC, but microcode (or micro-ops as Intel call them). The basic idea behind RISC is that the decoding is embedded directly in the instruction bits. CISC used to be the norm until the 90s. But embedding the decoding in the instruction is kind of tricky when your needs change (like memory-bus bottlenecks).
