On Wednesday, 16 September 2015 at 08:17:59 UTC, Don wrote:
I'm not convinced. I think they are downplaying the hardware
difficulties. Slide 34:
I don't think he is downplaying it. He has said that it will
probably take at least 10 years before it is available in
hardware. There is also a company called Rex Computing that are
looking at unum:
http://www.theplatform.net/2015/07/22/supercomputer-chip-startup-scores-funding-darpa-contract/
He assumes that you use a scratchpad (a big register file), not
caching, for intermediate calculations.
His basic reasoning is that brute force ubox methods makes for
highly parallel calculations. It might be possible to design ALUs
that can work with various unum bit widths efficiently (many
small or a few large)... who knows. You'll have to try first.
Let's not forget that there is a _lot_ of legacy constraints and
architectural assumptions in both x86 architecture.
The energy comparisons are plain dishonest. The power required
for accessing from DRAM is the energy consumption of a *cache
miss* !! What's the energy consumption of a load from cache?
I think this argument is aiming at HPC where you can find funding
for ASICs. They push a lot of data over the memory bus.
