Brian Padalino wrote: > Rebuilding an entire FPGA image on the fly isn't in the cards just > yet, though some high end Xilinx FPGAs do support "partial > reconfigurability" which will allow a design to have a standardized IO > interface and all the "guts" are reprogrammed without powering down > the device. > > This could allow, in theory, one "IO ring" to be made for the USRP and > the user would fill in the "guts" with their signal processing > application (eg: wideband TDMA, CDMA, narrowband FSK, etc). As long > as each of the guts had the same hooks to the outside, the FPGA can be > put into a state of lockdown while being reprogrammed, and a reset can > be applied to the guts once reprogrammed.
Not sure if USRP2 FPGA supports this or not. Not a bad idea to floor plan, get timing right, and lock down the non-DSP parts, and let the user create an inner application with abstract ports. But I'd be happy with a compile-time logically equivalent code organization. I think Matt's already planning for it. -- Johnathan Corgan Corgan Enterprises LLC http://corganenterprises.com _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org http://lists.gnu.org/mailman/listinfo/discuss-gnuradio
