On 10/29/07, Dan Halperin <[EMAIL PROTECTED]> wrote:
> In order for SDRs that think of their FPGA code as software (which I
> think has to be where this is going to realize its full power), it seems
> likely that we will need completely automated and reasonably fast ways
> to rebuild the FPGA on the fly. Do these exist?
Rebuilding an entire FPGA image on the fly isn't in the cards just
yet, though some high end Xilinx FPGAs do support "partial
reconfigurability" which will allow a design to have a standardized IO
interface and all the "guts" are reprogrammed without powering down
the device.
This could allow, in theory, one "IO ring" to be made for the USRP and
the user would fill in the "guts" with their signal processing
application (eg: wideband TDMA, CDMA, narrowband FSK, etc). As long
as each of the guts had the same hooks to the outside, the FPGA can be
put into a state of lockdown while being reprogrammed, and a reset can
be applied to the guts once reprogrammed.
The reprogramming time is on the order of milliseconds to hundreds of
milliseconds I believe, but I could be mistaken.
More information with regards to the Xilinx specific implementation
can be found here:
http://www.xilinx.com/products/design_tools/logic_design/advanced/partialreconfig.htm
Brian
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