On 04/07/2010 05:58 PM, Vikram Ragukumar wrote:
Matt,
Thank you for your email.
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
http://code.ettus.com/redmine/ettus/projects/fpga/repository/revisions/master/show/usrp2/simple_gemac
simple_gemac_wrapper in the fifo_2clock_cascade files.
which is instantiated in u2_core. Most of the buffering happens in I
would just start with the u2_core and simple_gemac_wrapper. If you're
not using the SERDES, that is a good place to start ripping out.
Does this imply that we can pull out the aeMB core, the 32K RAM and the
buffer pool under module u2_core ?
You can pull out whatever you want. Start from scratch if you like.
But if you take out the processor, you'll need to find some other way to
get the peripherals (DAC, clock gen, lsdac, etc.) programmed.
To carry out preliminary testing we need to be able to pass data to the
gemac and configure appropriate control registers. Could you please
suggest what existing modules we could reuse to send data to the gemac ?
You're going to need to look at the code. The processor does all that now.
Matt
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