Matt,
In our effort to distill the gemac core and related logic, we have
pulled out the following module under u2_core
SERDES, Dsp core, UART, external RAM interface and the buffer pool
The mac is all contained in simple_gemac, and above that in
simple_gemac_wrapper:
which is instantiated in u2_core. Most of the buffering happens in
simple_gemac_wrapper in the fifo_2clock_cascade files.
(a) Is any buffering for the gemac done using buffers in the buffer pool
or is it ok to eliminate that module all together ?
(b) The synthesis report currently shows that 24 BRAM's are being used
by the design. Does this sound about right ? Are there modules unrelated
to gemac or aeMB that we can pull out, to reduce BRAM usage ?
Thanks and Regards,
Vikram.
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