Just to place some previous experience I have, if you have diferent configuration parameters, the hardware, possibly, will not work!!! Same code without change nothing, and will not work. This is not a USRP issue, FPGA projects can go wrong with diferent parameters for synthesis.
2011/1/12 Matt Ettus <m...@ettus.com> > On 01/12/2011 12:31 PM, Gabriel Morel wrote: > >> Ok, I will compile the raw ethernet project for the USRP2 to be sure >> that I can modify it and use the modified version to my master. I was >> try to compile the project fpga.git under ISE10.1 and under ISE12.1. The >> two method compile well, give two different size of binary file, but >> both don't work in the USRP2. >> > > OK, so you chose the raw ethernet version. In reality, that is a bad > choice since all future development is on the other version. But fine, that > is what you chose. So now, stop using ISE 12, since I have told you that > ISE 12 will not work with the raw ethernet version. > > > > I compared the size of my two binary file with the binary file on the >> net, and the raw ethernet file on the net is the same size than my >> binary file maked under ISE12.1. This is why I ask for anybody to make >> same procedure than me to compare the data. I have to find the way to >> compile a good file of the raw ethernet version. >> > > File size is meaningless. Use "diff" or "md5sum" to tell if files are the > same or different. > > > But after some test, I can affirm that the problem is not the card, not >> the version of ISE and not the radio that I use. The problem can be the >> project under the repo git://ettus.sourcerepo.com/ettus/fpga.git, or >> maybe it's not the good repo. And it's not only for me, I think it's a >> major bug and it needs to be repair. >> > > There is no bug. I just built it myself and it works just fine. The bin > file should have an md5sum that starts with 3d4a. > > > > If you don't trust me, try it. Use Xilinx on Windows, create a project >> and put in all file of all different makefile in the repo for USRP2 with >> u2_rev3.v in top. Implement top module and create the bin file. After, >> give me some news plz. It's not loosing time, nobody had answer to my >> question and somebody have same problem than me. Thx a lot. >> > > Well, that is where you are going wrong. Don't create a project file. Use > the makefile as is. It works fine. The Xilinx tools are very picky and we > have everything set up just right. We also use them under linux which works > much better. > > Matt > > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > http://lists.gnu.org/mailman/listinfo/discuss-gnuradio >
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