Dear all,
I am using 30-day trial version of ISE 13.1 to get the RTL view of the standard FPGA configuration for USRP N200 in order to see what functionalities implemented in FPGA on USRP N200 board. The device I selected to do the simulation is exactly the FPGA chip used in USRP N200, XC3SD1800A, and the package is FG676. However, two mapping errors came up after synthesis, “Too many comps of types “SLICEL” found to fit this device.”, “The design is too large for the given device and package”. The number of occupied slices used exceeds what is available in this device. What is the problem here? The top module used in this simulation is u2p_c which is for USRP N200, and the chip used for this simulation is exactly the same type FPGA in USRP N200. Why the number of used SLICE exceeds what is available. How to get this problem addressed? I would really appreciate if anyone could offer me some hints or solutions to get this tackled. With thanks, Yan
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