Hello, I am working with a USRP X310 and am trying to increase the number of taps above the default limit of 41. The default RFNoC FIR filter is Xilinx coregen based and I am wondering if my new FIR filter will also have to be Xilinx coregen based. According to the attached data sheet the FIR filter should be able to support up to 2048 coefficients (table 1).
If it is possible to create an FIR filter using coregen that has more than 41 taps then will I also have to create a new IP module for the new RFNoC block? If it is not possible to create the filter should I write my own implementation in the 'User Code' section of the RFNoC block verilog file? Thank you, -William Healey
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