The short answer is, you can implement your block in any fashion you like. If you want to simply change the number of taps, simply editing our FIR filter (which the Xilinx coregen tools) is the easiest way to go. The number of taps (up to a degree) mostly depends on the available resources on your FPGA.
Cheers, Martin On 03/31/2016 08:06 AM, William Healey wrote: > Hello, > > I am working with a USRP X310 and am trying to increase the number of > taps above the default limit of 41. The default RFNoC FIR filter is > Xilinx coregen based and I am wondering if my new FIR filter will also > have to be Xilinx coregen based. According to the attached data sheet > the FIR filter should be able to support up to 2048 coefficients (table 1). > > If it is possible to create an FIR filter using coregen that has more > than 41 taps then will I also have to create a new IP module for the new > RFNoC block? > > If it is not possible to create the filter should I write my own > implementation in the 'User Code' section of the RFNoC block verilog file? > > Thank you, > -William Healey > > > _______________________________________________ > Discuss-gnuradio mailing list > Discuss-gnuradio@gnu.org > https://lists.gnu.org/mailman/listinfo/discuss-gnuradio > _______________________________________________ Discuss-gnuradio mailing list Discuss-gnuradio@gnu.org https://lists.gnu.org/mailman/listinfo/discuss-gnuradio
