On Sunday, 16 August 2020 12:46:53 BST Ralph Corderoy wrote:
> https://www.raspberrypi.org/documentation/hardware/raspberrypi/spi/README.md
> says
>
> The Raspberry Pi is equipped with one SPI bus that has 2 chip
> selects.
>
> so I'm assuming there's not another SPI bus which isn't normally enabled
> or allocated pins.
>
> But that seems to contradict with https://pinout.xyz/pinout/spi which
> shows
>
> SPI0: SCLK MOSI MISO CE0 CE1
> SPI1: SCLK MOSI MISO CE0 CE1 CE2
Ralph,
I raised all this on the Raspbery Pi Forum. The discussion is still ongoing,
but I think I have a handle on the situation, at a high level at least.
Out-of-the-Box the generic RPi has no SPI Buses, all of the Pins are used for
power, ground and GPIO functions. Other interfaces, such as I2C, 1-Wire and
SPI have to be enabled. This is achieved by editing a file in the /boot
partition to include overlays (these overlays cover everything from Real Time
Clock support to interfaces, including a lot of third-party add-ons, including
HATS). There are up to six SPI Busses, but availability depends on which RPi
you have (the jury's still out on which Pi has what).
However, there is another way to enable a limited number of interfaces. A
utility called raspi-config allows the SPI Bus to be enabled; this simply edits
the file in /boot on your behalf. It only offers one SPI Bus.
We are using a Rasperry Pi Zero for this application. This uses a pretty
recent Broadcom chip, but not as recent as the Raspberry Pi 4 (which it is
alleged supports all six busses). The Pi Zero can have two busses with two
chip selects on the default SPI0 and three on SPI1. However, although this
could allow us to do everything we want, I've seen enough plaintive postings
on the web about enabling these additional buses to be a bit wary of going
down that path.
On top of that the driver would need to be enhanced. As delivered I believe
it only supports SPI0 and one chip select, so I would have to add code to
support this plus code for SPI1 and three chip selects. I fear that this
would be a lot of work and may well be a hiding to nothing (bearing in mind
that my forte is not software development).
I have therefore all but decided to follow Ralph's suggestion to use hardware
to multiplex the chip selects to the different displays. I need to establish
whether buffering will be needed on the main bus lines too or if the fanout of
the Broadcom chip can cope with up to four or five devices connected. As I
understand it, the spec on GPIO pins is up to 16 mA per pin, with a maximum of
50 mA on all pins, so it will depend on the input current of the SPI Bus chip
on the display devices.
Thanks for your help.
--
Terry Coles
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