From: CK Hu <ck...@mediatek.com>
This patch adds the device nodes for the HDMI encoder, HDMI PHY,
and HDMI CEC modules.
Signed-off-by: CK Hu <ck.hu at mediatek.com>
Signed-off-by: Cawa Cheng <cawa.cheng at mediatek.com>
Signed-off-by: Jie Qiu <jie.qiu at mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz at chromium.org>
Signed-off-by: Philipp Zabel <p.zabel at pengutronix.de>
---
Changes since v4:
- Drop mediatek,cec DT property
- Add mediatek, prefix to ibias DT properties
- Remove ddc-i2c-bus property, that goes into the
board specific connector node
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 71 ++++++++++++++++++++++++++++++++
1 file changed, 71 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 9874ab1..2eb5ca1 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -199,6 +199,30 @@
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
+ hdmi_pin: xxx {
+
+ /*hdmi htplg pin*/
+ pins1 {
+ pinmux =
<MT8173_PIN_21_HTPLG__FUNC_HTPLG>;
+ input-enable;
+ bias-pull-down;
+ };
+
+ /*hdmi flt 5v pin*/
+ pins2 {
+ pinmux =
<MT8173_PIN_42_DSI_TE__FUNC_GPIO42>;
+ input-enable;
+ bias-pull-up;
+ };
+
+ /*hdmi 5v pin*/
+ pins3 {
+ pinmux =
<MT8173_PIN_127_LCM_RST__FUNC_GPIO127>;
+ output-enable;
+ bias-pull-up;
+ };
+ };
+
i2c0_pins_a: i2c0 {
pins1 {
pinmux =
<MT8173_PIN_45_SDA0__FUNC_SDA0>,
@@ -275,6 +299,13 @@
clock-names = "spi", "wrap";
};
+ cec: cec at 10013000 {
+ compatible = "mediatek,mt8173-cec";
+ reg = <0 0x10013000 0 0xbc>;
+ interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&infracfg CLK_INFRA_CEC>;
+ };
+
sysirq: intpol-controller at 10200620 {
compatible = "mediatek,mt8173-sysirq",
"mediatek,mt6577-sysirq";
@@ -301,6 +332,16 @@
#clock-cells = <1>;
};
+ hdmi_phy: hdmi-phy at 10209100 {
+ compatible = "mediatek,mt8173-hdmi-phy";
+ reg = <0 0x10209100 0 0x24>;
+ clocks = <&apmixedsys CLK_APMIXED_HDMI_REF>;
+ clock-names = "pll_ref";
+ mediatek,ibias = <0xa>;
+ mediatek,ibias_up = <0x1c>;
+ #phy-cells = <0>;
+ };
+
mipi_tx0: mipi-dphy at 10215000 {
compatible = "mediatek,mt8173-mipi-tx";
reg = <0 0x10215000 0 0x1000>;
@@ -808,6 +849,36 @@
clock-names = "apb", "smi";
};
+ hdmi0: hdmi at 14025000 {
+ compatible = "mediatek,mt8173-hdmi";
+ reg = <0 0x14025000 0 0x400>;
+ interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&mmsys CLK_MM_HDMI_PIXEL>,
+ <&mmsys CLK_MM_HDMI_PLLCK>,
+ <&mmsys CLK_MM_HDMI_AUDIO>,
+ <&mmsys CLK_MM_HDMI_SPDIF>;
+ clock-names = "pixel", "pll", "bclk", "spdif";
+ pinctrl-names = "default";
+ pinctrl-0 = <&hdmi_pin>;
+ phys = <&hdmi_phy>;
+ phy-names = "hdmi";
+ mediatek,syscon-hdmi = <&mmsys 0x900>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 0 {
+ reg = <0>;
+
+ hdmi0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+ };
+ };
+
larb4: larb at 14027000 {
compatible = "mediatek,mt8173-smi-larb";
reg = <0 0x14027000 0 0x1000>;
--
2.6.1
