fsl-dcu not works on latest "drm-next"

[Meng Yi]

Hi Alexander,

> From your backtrace I guess wait_event_timeout is called in some atomic
> context (might_sleep(); is called inside wait_event_timeout). This has nothing
> to do with regmap.
> 

Here is my view of point:
Since IRQ setup codes using regmap, and which is not setup properly, so 
wait_event_timeout.

> 
> The inital problem came up with 922a9f936e40001f9b921379aab90047d5990923
> ("regmap: mmio: Convert to regmap_bus and fix accessor usage"). The
> commits 9f9f8b863ad130ec0c25f378bdbad64ba71291de,
> 4f7d6dd4df8b388e2056c89b528254cdd79dea2a and
> 0dbdb76c0ca8e7caf27c9a210f64c4359e2974a4 tried to fix that. With those I
> could successfully probe DCU.

Thanks for your information.
DCU was able to  be probed without those patches, and DCU still not works with 
those patches.

And here is my DTS and regmap_config,

Specified "big-endian" in DTS,

        dcu: dcu at 2ce0000 {
            compatible = "fsl,ls1021a-dcu";
            reg = <0x0 0x2ce0000 0x0 0x10000>;
            interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
            clocks = <&platform_clk 0>;
            clock-names = "dcu";
            big-endian;
            status = "disabled";
        };

I can't tell the difference of "reg_format_endian" and " val_format_endian ", 
so I had tried four conditions.

static const struct regmap_config fsl_dcu_regmap_config = {
    .reg_bits = 32,
    .reg_stride = 4,
    .val_bits = 32,
    .cache_type = REGCACHE_RBTREE,
//  .reg_format_endian = REGMAP_ENDIAN_BIG,
//  .val_format_endian = REGMAP_ENDIAN_BIG,

    .volatile_reg = fsl_dcu_drm_is_volatile_reg,
};

Thanks,
Best Regards,
Meng Yi