On Tue, 15 Aug 2017 16:47:18 -0700
Eric Anholt <e...@anholt.net> wrote:
> We want the adjusted_mode->clock to be the actual clock we're
> expecting to program, so that consumers see the right values for clock
> and vrefresh.
>
> Signed-off-by: Eric Anholt <e...@anholt.net>
Reviewed-by: Boris Brezillon <boris.brezil...@free-electrons.com>
> ---
> drivers/gpu/drm/vc4/vc4_dsi.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_dsi.c b/drivers/gpu/drm/vc4/vc4_dsi.c
> index d1e0dc908048..eb787eed8abe 100644
> --- a/drivers/gpu/drm/vc4/vc4_dsi.c
> +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
> @@ -859,11 +859,7 @@ static bool vc4_dsi_encoder_mode_fixup(struct
> drm_encoder *encoder,
> pll_clock = parent_rate / divider;
> pixel_clock_hz = pll_clock / dsi->divider;
>
> - /* Round up the clk_set_rate() request slightly, since
> - * PLLD_DSI1 is an integer divider and its rate selection will
> - * never round up.
> - */
> - adjusted_mode->clock = pixel_clock_hz / 1000 + 1;
> + adjusted_mode->clock = pixel_clock_hz / 1000;
>
> /* Given the new pixel clock, adjust HFP to keep vrefresh the same. */
> adjusted_mode->htotal = pixel_clock_hz / (mode->vrefresh *
> mode->vtotal);
> @@ -900,7 +896,11 @@ static void vc4_dsi_encoder_enable(struct drm_encoder
> *encoder)
> vc4_dsi_dump_regs(dsi);
> }
>
> - phy_clock = pixel_clock_hz * dsi->divider;
> + /* Round up the clk_set_rate() request slightly, since
> + * PLLD_DSI1 is an integer divider and its rate selection will
> + * never round up.
> + */
> + phy_clock = (pixel_clock_hz + 1000) * dsi->divider;
> ret = clk_set_rate(dsi->pll_phy_clock, phy_clock);
> if (ret) {
> dev_err(&dsi->pdev->dev,
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