On Fri, Oct 20, 2017 at 09:49:22AM +0200, Boris Brezillon wrote:
> Document the bindings used for the Cadence DSI bridge.
>
> Signed-off-by: Boris Brezillon <boris.brezil...@free-electrons.com>
> ---
> Hi Rob,
>
> I dropped your A-b because two important things changed in this
> version:
> * the clk names have changed (they are now prefixed with dsi_)
> * compatible no longer contains the IP version
>
> Feel free to add it back.
>
> Regards,
>
> Boris
>
> Changes in v4:
> - Rename DSI clks (suggested by Tomi)
> - Drop the IP version in the compatible since it can be extracted from
> a register (suggested by Andrzej)
>
> Changes in v3:
> - Fix clock names in the example
> - Document how to represent DSI devices that are controller through
> an external bus like I2C or SPI
>
> Changes in v2:
> - None
> ---
> .../bindings/display/bridge/cdns,dsi.txt | 109
> +++++++++++++++++++++
> 1 file changed, 109 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> new file mode 100644
> index 000000000000..50bb3189f2ee
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
> @@ -0,0 +1,109 @@
> +Cadence DSI bridge
> +==================
> +
> +The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes.
> +
> +Required properties:
> +- compatible: should be set to "cdns,dsi".
> +- reg: physical base address and length of the controller's registers.
> +- interrupts: interrupt line connected to the DSI bridge.
> +- clocks: DSI bridge clocks.
> +- clock-names: must contain "dsi_p_clk" and "dsi_sys_clk".
> +- phys: phandle link to the MIPI D-PHY controller.
> +- phy-names: must contain "dphy".
> +- #address-cells: must be set to 1.
> +- #size-cells: must be set to 0.
> +
> +Required subnodes:
> +- ports: Ports as described in Documentation/devicetree/bindings/graph.txt.
> + 2 ports are available:
> + * port 0: this port is only needed if some of your DSI devices are
> + controlled through an external bus like I2C or SPI. Can have at
> + most 4 endpoints. The endpoint number is directly encoding the
> + DSI virtual channel used by this device.
> + * port 1: represents the DPI input.
> + Other ports will be added later to support the new kind of inputs.
> +
> +- one subnode per DSI device connected on the DSI bus. Each DSI device should
> + contain a reg property encoding its virtual channel.
> +
> +Example:
> +
> + dsi0: dsi@fd0c0000 {
> + compatible = "cdns,dsi-1.3.1";
> + reg = <0x0 0xfd0c0000 0x0 0x1000>;
> + clocks = <&pclk>, <&sysclk>;
> + clock-names = "dsi_p_clk", "dsi_sys_clk";
> + interrupts = <1>;
> + phys = <&dphy1>;
> + phy-names = "dphy";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + dsi0_dpi_input: endpoint {
> + remote-endpoint = <&xxx_dpi_output>;
> + };
> + };
> + };
> +
> + panel: dsi-dev@0 {
> + compatible = "<vendor,panel>";
> + reg = <0>;
> + };
> + };
> +
> +or
> +
> + dsi0: dsi@fd0c0000 {
> + compatible = "cdns,dsi";
> + reg = <0x0 0xfd0c0000 0x0 0x1000>;
> + clocks = <&pclk>, <&sysclk>;
> + clock-names = "sys_p_clk", "dsi_sys_clk";
Needs updating?
With that,
Acked-by: Rob Herring <r...@kernel.org>
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