Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse <jcro...@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 121 +++++++++++++++++++++++++++
 1 file changed, 121 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi 
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index cdaabeb3c995..10db0ceb3699 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -192,6 +192,59 @@
                method = "smc";
        };
 
+gpu_opp_table: adreno-opp-table {
+               compatible = "operating-points-v2-qcom-level";
+
+               opp-710000000 {
+                       opp-hz = /bits/ 64 <710000000>;
+                       qcom,level = <416>;
+               };
+
+               opp-675000000 {
+                       opp-hz = /bits/ 64 <675000000>;
+                       qcom,level = <384>;
+               };
+
+               opp-596000000 {
+                       opp-hz = /bits/ 64 <596000000>;
+                       qcom,level = <320>;
+               };
+
+               opp-520000000 {
+                       opp-hz = /bits/ 64 <520000000>;
+                       qcom,level = <256>;
+               };
+
+               opp-414000000 {
+                       opp-hz = /bits/ 64 <414000000>;
+                       qcom,level = <192>;
+               };
+
+               opp-342000000 {
+                       opp-hz = /bits/ 64 <342000000>;
+                       qcom,level = <128>;
+               };
+
+               opp-257000000 {
+                       opp-hz = /bits/ 64 <257000000>;
+                       qcom,level = <64>;
+               };
+       };
+
+       gmu_opp_table: adreno-gmu-opp-table {
+               compatible = "operating-points-v2-qcom-level";
+
+               opp-400000000 {
+                       opp-hz = /bits/ 64 <400000000>;
+                       qcom,level = <128>;
+               };
+
+               opp-200000000 {
+                       opp-hz = /bits/ 64 <200000000>;
+                       qcom,level = <48>;
+               };
+       };
+
        soc: soc {
                #address-cells = <1>;
                #size-cells = <1>;
@@ -323,5 +376,73 @@
                                status = "disabled";
                        };
                };
+
+               adreno_smmu: adreno-smmu@5040000 {
+                       compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
+                       reg = <0x5040000 0x10000>;
+                       #iommu-cells = <1>;
+                       #global-interrupts = <2>;
+                       interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+                                       <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+                                       <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+                       clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+                               <&gcc GCC_GPU_CFG_AHB_CLK>;
+                       clock-names = "bus", "iface";
+
+                       power-domains = <&gpucc GPU_CX_GDSC>;
+               };
+
+               gpu@5000000 {
+                       compatible = "qcom,adreno-630.2", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0x5000000 0x40000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       /*
+                        * Look ma, no clocks! The GPU clocks and power are
+                        * controlled entirely by the GMU
+                        */
+
+                       interrupts = <0 300 0>;
+                       interrupt-names = "kgsl_3d0_irq";
+
+                       iommus = <&adreno_smmu 0>;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       qcom,gmu = <&gmu>;
+               };
+
+               gmu: gmu@506a000 {
+                       compatible="qcom,adreno-gmu";
+
+                       reg = <0x506a000 0x30000>,
+                               <0xb280000 0x10000>,
+                               <0xb480000 0x10000>;
+                       reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
+
+                       interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "hfi", "gmu";
+
+                       clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+                               <&gpucc GPU_CC_CXO_CLK>,
+                               <&gcc GCC_DDRSS_GPU_AXI_CLK>,
+                               <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
+                       clock-names = "gmu", "cxo", "axi", "memnoc";
+
+                       power-domains = <&gpucc GPU_CX_GDSC>;
+                       iommus = <&adreno_smmu 5>;
+
+                       operating-points-v2 = <&gmu_opp_table>;
+               };
        };
 };
-- 
2.18.0

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