https://bugs.freedesktop.org/show_bug.cgi?id=108591
Martin Peres <martin.pe...@free.fr> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|RESOLVED |CLOSED
--- Comment #11 from Martin Peres <martin.pe...@free.fr> ---
(In reply to Chris Wilson from comment #10)
> commit 7fa28e146994da1e8a4124623d7da97b798ea520 (HEAD ->
> drm-intel-next-queued, drm-intel/for-linux-next,
> drm-intel/drm-intel-next-queued)
> Author: Chris Wilson <ch...@chris-wilson.co.uk>
> Date: Mon Nov 19 15:41:53 2018 +0000
>
> drm/i915: Write GPU relocs harder with gen3
>
> Under moderate amounts of GPU stress, we can observe on Bearlake and
> Pineview (later gen3 models) that we execute the following batch buffer
> before the write into the batch is coherent. Adding extra (tested with
> upto 32x) MI_FLUSH to either the invalidation, flush or both phases does
> not solve the incoherency issue with the relocations, but emitting the
> MI_STORE_DWORD_IMM twice does. So be it.
>
> Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing")
> Testcase: igt/gem_tiled_fence_blits # blb/pnv
> Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Reviewed-by: Joonas Lahtinen <joonas.lahti...@linux.intel.com>
> Link:
> https://patchwork.freedesktop.org/patch/msgid/20181119154153.15327-1-
> ch...@chris-wilson.co.uk
Oddly-enough, this was not sufficient to fix the issue, but it stopped failing
after drmtip_176
(https://intel-gfx-ci.01.org/tree/drm-tip/drmtip_176/fi-gdg-551/igt@gem_tiled_fence_bl...@normal.html),
so closing!
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