On Thu, 10 Jan 2019 15:10:48 +0000 Peter Rosin <p...@axentia.se> wrote:
> The A2Q and UPDATE bits have no effect in the channel disable registers. > However, since they are present, assume that the intention is to disable > planes, not immediately as indicated by the RST bit, but on the next > frame shift since that is what A2Q and UPDATE means in the channel enable > registers. > > Disabling the plane on the next frame shift is done with the EN bit, > so use that. It's been a long time, but I think I had a good reason for forcing a reset. IIRC, when you don't do that and the CRTC is disabled before the plane, the EN bit stays around, and next time you queue a plane update, you'll start with an invalid buf pointer. > > Signed-off-by: Peter Rosin <p...@axentia.se> > --- > drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c > b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c > index 05519e8c6586..f2f570642f84 100644 > --- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c > +++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_plane.c > @@ -728,9 +728,7 @@ static void atmel_hlcdc_plane_atomic_disable(struct > drm_plane *p, > > /* Disable the layer */ > atmel_hlcdc_layer_write_reg(&plane->layer, ATMEL_HLCDC_LAYER_CHDR, > - ATMEL_HLCDC_LAYER_RST | > - ATMEL_HLCDC_LAYER_A2Q | > - ATMEL_HLCDC_LAYER_UPDATE); > + ATMEL_HLCDC_LAYER_EN); > > /* Clear all pending interrupts */ > atmel_hlcdc_layer_read_reg(&plane->layer, ATMEL_HLCDC_LAYER_ISR); _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
