The burst mode panels with 4-lane would require to enable trail bits in DSI basic control register.
So, enable 2byte trail and trail_env for 4-lane burst mode devices. Allwinner A64 BSP should also relie on same setup for enabling trail bit in DSI controller. Reference code avialable in BSP (from linux-sunxi/ drivers/video/sunxi/disp2/disp/de/lowlevel_sun50iw1/de_dsi.c) if (panel->lcd_dsi_lane == 4) { dsi_dev[sel]->dsi_basic_ctl.bits.trail_inv = 0xc; dsi_dev[sel]->dsi_basic_ctl.bits.trail_fill = 1; } Signed-off-by: Jagan Teki <ja...@amarulasolutions.com> Tested-by: Merlijn Wajer <merl...@wizzup.org> --- drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c index 46ad142e66e8..a2ad9fa7f8d5 100644 --- a/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c +++ b/drivers/gpu/drm/sun4i/sun6i_mipi_dsi.c @@ -33,6 +33,8 @@ #define SUN6I_DSI_CTL_EN BIT(0) #define SUN6I_DSI_BASIC_CTL_REG 0x00c +#define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n) (((n) & 0xf) << 4) +#define SUN6I_DSI_BASIC_CTL_TRAIL_FILL BIT(3) #define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2) #define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1) #define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0) @@ -464,6 +466,10 @@ static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, /* enable burst mode */ regmap_read(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, &val); val |= SUN6I_DSI_BASIC_CTL_VIDEO_BURST; + if (device->lanes == 4) { + val |= SUN6I_DSI_BASIC_CTL_TRAIL_INV(0xc); + val |= SUN6I_DSI_BASIC_CTL_TRAIL_FILL; + } regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, val); } -- 2.18.0.321.gffc6fa0e3 _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel