Hi Brian, > Since your first patch set, I did raise this internally. The request > has been making it's way through: > > - GPU engineering, to determine what exactly this format is, and > what other variants there might be which are supported on different > GPU generations, so that we can determine a sane naming convention. > > - Our legal team, to determine what detail we are happy to share from > an IP perspective. I can't imagine there being an issue here, but > process is process, and there's not a lot I can do to move that > along. > > There was talk on the legal side last week. I will ask for an update. > I realise this is taking a very long time, and for that I can only > apologise; I really am trying to get you an answer.
Thanks for the update and your effort to make a generic solution on the ARM side. It's really some time passed since last time we talked about this, but I think it's worth to wait for more time to get a reliable solution with more internal information known by us. > For other layouts which don't have this kind of combinatorial effect, > I'd rather have #defines for the specific layouts, all individually > setting the top bit, without giving that top bit any kind of "name". > The top bit would effectively mean "not AFBC", rather than meaning > "AGTB", allowing us to use the lower bits more freely. > Seems like another kind of category, but with different meaning. > If you can hang on a while longer, I hope Arm can push a patch which > you can just use directly, and then handling the bit assignments will > be our mess rather than yours :-) > That's better, I can wait :-) Thanks, Qiang > > +#define DRM_FORMAT_MOD_ARM_CODE(type, val) \ > > + fourcc_mod_code(ARM, ((__u64)type << 48) | ((val) & > > 0x0000ffffffffffffULL)) > > + > > /* > > * Arm Framebuffer Compression (AFBC) modifiers > > * > > @@ -615,7 +628,8 @@ extern "C" { > > * Further information on the use of AFBC modifiers can be found in > > * Documentation/gpu/afbc.rst > > */ > > -#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) fourcc_mod_code(ARM, > > __afbc_mode) > > +#define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \ > > + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode) > > > > /* > > * AFBC superblock size > > @@ -709,6 +723,21 @@ extern "C" { > > */ > > #define AFBC_FORMAT_MOD_BCH (1ULL << 11) > > > > +/* > > + * Arm Graphics Tiled Buffer (AGTB) modifiers > > + */ > > +#define DRM_FORMAT_MOD_ARM_AGTB(mode) \ > > + DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AGTB, mode) > > + > > +/* > > + * AGTB mode 0 modifier > > + * > > + * This is used by ARM Mali Utgard/Midgard GPU. It divides buffer into > > + * 16x16 pixel blocks. Blocks are stored linearly in order, but pixels > > + * in the block are reordered. > > + */ > > +#define DRM_FORMAT_MOD_ARM_AGTB_MODE0 DRM_FORMAT_MOD_ARM_AGTB(1) > > + > > /* > > * Allwinner tiled modifier > > * > > -- > > 2.17.1 > > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel