On 09/08/2019 22:09, Alyssa Rosenzweig wrote:
> While newer kbase include only the numbers of errata, older kbase
> releases included one-line descriptions for each errata, which is useful
> for those working on the driver. Import these descriptions. Most are
> from kbase verbatim; a few I edited for clarity.
>
> v2: Wrote a description for the workaround of an issue whose cause is
> still unknown (Stephen). Errata which pertain to newer models
s/Stephen/Steven/
> unsupported by the mainline driver, for which Arm has not yet released
> errata information, have been removed from the issue list as the kernel
> need not concern itself with these.
I'm not sure it's worth removing the errata that Panfrost doesn't yet
support. The Arm release kernel drivers[1] do use these symbols so it is
vaguely public what the errata are.
For example HW_ISSUE_TGOX_R1_1234:
> if (kbase_hw_has_issue(kbdev, BASE_HW_ISSUE_TGOX_R1_1234)) {
> if (katom->atom_flags &
> KBASE_KATOM_FLAG_HOLDING_L2_REF_PROT) {
> kbase_pm_protected_l2_override(kbdev, false);
> katom->atom_flags &=
> ~KBASE_KATOM_FLAG_HOLDING_L2_REF_PROT;
> }
> }
It's a workaround for protected mode handling on Mali-G31. Admittedly
protected mode is probably not going to be high up on the Panfrost TODO
list... :)
Steve
[1]
https://developer.arm.com/tools-and-software/graphics-and-gaming/mali-drivers/midgard-kernel
> Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzw...@collabora.com>
> ---
> drivers/gpu/drm/panfrost/panfrost_issues.h | 106 +++++++++++++++------
> 1 file changed, 78 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/panfrost/panfrost_issues.h
> b/drivers/gpu/drm/panfrost/panfrost_issues.h
> index cec6dcdad..36e503614 100644
> --- a/drivers/gpu/drm/panfrost/panfrost_issues.h
> +++ b/drivers/gpu/drm/panfrost/panfrost_issues.h
> @@ -13,37 +13,101 @@
> * to care about.
> */
> enum panfrost_hw_issue {
> + /* Need way to guarantee that all previously-translated memory accesses
> + * are commited */
> HW_ISSUE_6367,
> +
> + /* On job complete with non-done the cache is not flushed */
> HW_ISSUE_6787,
> +
> + /* Write of PRFCNT_CONFIG_MODE_MANUAL to PRFCNT_CONFIG causes a
> + * instrumentation dump if PRFCNT_TILER_EN is enabled */
> HW_ISSUE_8186,
> +
> + /* TIB: Reports faults from a vtile which has not yet been allocated */
> HW_ISSUE_8245,
> +
> + /* uTLB deadlock could occur when writing to an invalid page at the
> + * same time as access to a valid page in the same uTLB cache line ( ==
> + * 4 PTEs == 16K block of mapping) */
> HW_ISSUE_8316,
> +
> + /* HT: TERMINATE for RUN command ignored if previous LOAD_DESCRIPTOR is
> + * still executing */
> HW_ISSUE_8394,
> +
> + /* CSE: Sends a TERMINATED response for a task that should not be
> + * terminated */
> HW_ISSUE_8401,
> +
> + /* Repeatedly Soft-stopping a job chain consisting of (Vertex Shader,
> + * Cache Flush, Tiler) jobs causes DATA_INVALID_FAULT on tiler job. */
> HW_ISSUE_8408,
> +
> + /* Disable the Pause Buffer in the LS pipe. */
> HW_ISSUE_8443,
> +
> + /* Change in RMUs in use causes problems related with the core's SDC */
> HW_ISSUE_8987,
> +
> + /* Compute endpoint has a 4-deep queue of tasks, meaning a soft stop
> + * won't complete until all 4 tasks have completed */
> HW_ISSUE_9435,
> +
> + /* HT: Tiler returns TERMINATED for non-terminated command */
> HW_ISSUE_9510,
> +
> + /* Occasionally the GPU will issue multiple page faults for the same
> + * address before the MMU page table has been read by the GPU */
> HW_ISSUE_9630,
> +
> + /* RA DCD load request to SDC returns invalid load ignore causing
> + * colour buffer mismatch */
> HW_ISSUE_10327,
> +
> + /* MMU TLB invalidation hazards */
> HW_ISSUE_10649,
> +
> + /* Missing cache flush in multi core-group configuration */
> HW_ISSUE_10676,
> +
> + /* Chicken bit on T72X for a hardware workaround in compiler */
> HW_ISSUE_10797,
> +
> + /* Soft-stopping fragment jobs might fail with TILE_RANGE_FAULT */
> HW_ISSUE_10817,
> +
> + /* Intermittent missing interrupt on job completion */
> HW_ISSUE_10883,
> +
> + /* Soft-stopping fragment jobs might fail with TILE_RANGE_ERROR
> + * (similar to issue 10817) and can use #10817 workaround */
> HW_ISSUE_10959,
> +
> + /* Soft-stopped fragment shader job can restart with out-of-bound
> + * restart index */
> HW_ISSUE_10969,
> +
> + /* Race condition can cause tile list corruption */
> HW_ISSUE_11020,
> +
> + /* Write buffer can cause tile list corruption */
> HW_ISSUE_11024,
> +
> + /* Pause buffer can cause a fragment job hang */
> HW_ISSUE_11035,
> - HW_ISSUE_11056,
> +
> + /* Clear encoder state for a hard stopped fragment job which is AFBC
> + * encoded by soft resetting the GPU. Only for T76X r0p0, r0p1 and
> + * r0p1_50rel0 */
> HW_ISSUE_T76X_3542,
> +
> + /* Keep tiler module clock on to prevent GPU stall */
> HW_ISSUE_T76X_3953,
> - HW_ISSUE_TMIX_8463,
> +
> + /* Don't set SC_LS_ATTR_CHECK_DISABLE/SC_LS_ALLOW_ATTR_TYPES */
> GPUCORE_1619,
> - HW_ISSUE_TMIX_8438,
> - HW_ISSUE_TGOX_R1_1234,
> +
> HW_ISSUE_END
> };
>
> @@ -59,9 +123,7 @@ enum panfrost_hw_issue {
> BIT_ULL(HW_ISSUE_10676) | \
> BIT_ULL(HW_ISSUE_10883) | \
> BIT_ULL(HW_ISSUE_11020) | \
> - BIT_ULL(HW_ISSUE_11035) | \
> - BIT_ULL(HW_ISSUE_11056) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_11035))
>
> #define hw_issues_t600_r0p0_15dev0 (\
> BIT_ULL(HW_ISSUE_8186) | \
> @@ -78,9 +140,7 @@ enum panfrost_hw_issue {
> #define hw_issues_t620 (\
> BIT_ULL(HW_ISSUE_10649) | \
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_10959) | \
> - BIT_ULL(HW_ISSUE_11056) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_10959))
>
> #define hw_issues_t620_r0p1 (\
> BIT_ULL(HW_ISSUE_10327) | \
> @@ -97,14 +157,11 @@ enum panfrost_hw_issue {
> #define hw_issues_t720 (\
> BIT_ULL(HW_ISSUE_10649) | \
> BIT_ULL(HW_ISSUE_10797) | \
> - BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_11056) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_10883))
>
> #define hw_issues_t760 (\
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_T76X_3953) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_T76X_3953))
>
> #define hw_issues_t760_r0p0 (\
> BIT_ULL(HW_ISSUE_11020) | \
> @@ -129,36 +186,29 @@ enum panfrost_hw_issue {
>
> #define hw_issues_t820 (\
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_T76X_3953) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_T76X_3953))
>
> #define hw_issues_t830 (\
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_T76X_3953) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_T76X_3953))
>
> #define hw_issues_t860 (\
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_T76X_3953) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_T76X_3953))
>
> #define hw_issues_t880 (\
> BIT_ULL(HW_ISSUE_10883) | \
> - BIT_ULL(HW_ISSUE_T76X_3953) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> + BIT_ULL(HW_ISSUE_T76X_3953))
>
> #define hw_issues_g31 0
>
> -#define hw_issues_g31_r1p0 (\
> - BIT_ULL(HW_ISSUE_TGOX_R1_1234))
> +#define hw_issues_g31_r1p0 0
>
> #define hw_issues_g51 0
>
> #define hw_issues_g52 0
>
> -#define hw_issues_g71 (\
> - BIT_ULL(HW_ISSUE_TMIX_8463) | \
> - BIT_ULL(HW_ISSUE_TMIX_8438))
> +#define hw_issues_g71 0
>
> #define hw_issues_g71_r0p0_05dev0 (\
> BIT_ULL(HW_ISSUE_T76X_3953))
>
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