Hi, On 18/11/2019 16:25, Adrian Ratiu wrote:
A small commit log would be welcome here. > Signed-off-by: Sjoerd Simons <sjoerd.sim...@collabora.com> > Signed-off-by: Martyn Welch <martyn.we...@collabora.com> > Signed-off-by: Adrian Ratiu <adrian.ra...@collabora.com> > --- > .../bindings/display/imx/mipi-dsi.txt | 56 +++++++++++++++++++ > 1 file changed, 56 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/imx/mipi-dsi.txt > > diff --git a/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt > b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt > new file mode 100644 > index 000000000000..3f05c32ef963 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/imx/mipi-dsi.txt New bindings should use the yaml dt-schema format, could you convert it ? Neil > @@ -0,0 +1,56 @@ > +Freescale i.MX6 DW MIPI DSI Host Controller > +=========================================== > + > +The DSI host controller is a Synopsys DesignWare MIPI DSI v1.01 IP > +with a companion PHY IP. > + > +These DT bindings follow the Synopsys DW MIPI DSI bindings defined in > +Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with > +the following device-specific properties. > + > +Required properties: > + > +- #address-cells: Should be <1>. > +- #size-cells: Should be <0>. > +- compatible: "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi". > +- reg: See dw_mipi_dsi.txt. > +- interrupts: The controller's CPU interrupt. > +- clocks, clock-names: Phandles to the controller's pll reference > + clock(ref) and APB clock(pclk), as described in [1]. > +- ports: a port node with endpoint definitions as defined in [2]. > +- gpr: Should be <&gpr>. > + Phandle to the iomuxc-gpr region containing the multiplexer > + control register. > + > +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt > +[2] Documentation/devicetree/bindings/media/video-interfaces.txt > + > +Example: > + > + mipi_dsi: mipi@21e0000 { > + #address-cells = <1>; > + #size-cells = <0>; > + compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi"; > + reg = <0x021e0000 0x4000>; > + interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>; > + gpr = <&gpr>; > + clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>, > + <&clks IMX6QDL_CLK_MIPI_IPG>; > + clock-names = "ref", "pclk"; > + status = "okay"; > + > + ports { > + port@0 { > + reg = <0>; > + mipi_mux_0: endpoint { > + remote-endpoint = <&ipu1_di0_mipi>; > + }; > + }; > + port@1 { > + reg = <1>; > + mipi_mux_1: endpoint { > + remote-endpoint = <&ipu1_di1_mipi>; > + }; > + }; > + }; > + }; > _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel