On 2020-06-24 15:02, Mark Brown wrote: > On Wed, Jun 24, 2020 at 04:45:28PM +0300, Andy Shevchenko wrote: >> On Wed, Jun 24, 2020 at 4:27 PM Mark Brown <broo...@kernel.org> wrote: > >>> As I said down the thread that's not a great pattern since it means that >>> probe deferral errors never get displayed and users have a hard time >>> figuring out why their driver isn't instantiating. > >> Don't we have a file in the debugfs to list deferred drivers? > > Part of what this patch series aims to solve is that that list is not > very useful since it doesn't provide any information on how things got > deferred which means it's of no use in trying to figure out any > problems. > >> In the case of deferred probes the errors out of it makes users more >> miserable in order to look through tons of spam and lose really useful >> data in the logs. > > I seem to never manage to end up using any of the systems which generate > excessive deferrals.
Be thankful... And count me in as one of those miserable users; here's one of mine being bad enough without even printing any specific messages about deferring ;) Robin. ----- [robin@weasel-cheese ~]$ dmesg | grep dwmmc [ 3.046297] dwmmc_rockchip ff0c0000.mmc: IDMAC supports 32-bit address mode. [ 3.054312] dwmmc_rockchip ff0c0000.mmc: Using internal DMA controller. [ 3.061774] dwmmc_rockchip ff0c0000.mmc: Version ID is 270a [ 3.068101] dwmmc_rockchip ff0c0000.mmc: DW MMC controller at irq 30,32 bit host data width,256 deep fifo [ 3.079638] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 3.087678] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 3.095134] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 3.101480] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 3.113071] dwmmc_rockchip ff0f0000.mmc: IDMAC supports 32-bit address mode. [ 3.121110] dwmmc_rockchip ff0f0000.mmc: Using internal DMA controller. [ 3.128565] dwmmc_rockchip ff0f0000.mmc: Version ID is 270a [ 3.134886] dwmmc_rockchip ff0f0000.mmc: DW MMC controller at irq 32,32 bit host data width,256 deep fifo [ 3.948510] dwmmc_rockchip ff0c0000.mmc: IDMAC supports 32-bit address mode. [ 3.956475] dwmmc_rockchip ff0c0000.mmc: Using internal DMA controller. [ 3.963884] dwmmc_rockchip ff0c0000.mmc: Version ID is 270a [ 3.970133] dwmmc_rockchip ff0c0000.mmc: DW MMC controller at irq 30,32 bit host data width,256 deep fifo [ 4.141231] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 4.149178] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 4.156582] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 4.162823] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 4.175606] dwmmc_rockchip ff0f0000.mmc: IDMAC supports 32-bit address mode. [ 4.183540] dwmmc_rockchip ff0f0000.mmc: Using internal DMA controller. [ 4.190946] dwmmc_rockchip ff0f0000.mmc: Version ID is 270a [ 4.197196] dwmmc_rockchip ff0f0000.mmc: DW MMC controller at irq 32,32 bit host data width,256 deep fifo [ 4.250758] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 4.258688] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 4.266104] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 4.272358] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 4.285390] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 4.293333] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 4.300750] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 4.307005] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 4.971373] dwmmc_rockchip ff0f0000.mmc: Successfully tuned phase to 134 [ 5.027225] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 5.035339] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 5.042769] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 5.049050] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 24.727583] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 24.745541] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 24.753003] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 24.763289] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 25.589620] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 25.603066] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 25.615283] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 25.627911] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 25.643469] dwmmc_rockchip ff0d0000.mmc: IDMAC supports 32-bit address mode. [ 25.651532] dwmmc_rockchip ff0d0000.mmc: Using internal DMA controller. [ 25.658960] dwmmc_rockchip ff0d0000.mmc: Version ID is 270a [ 25.665246] dwmmc_rockchip ff0d0000.mmc: DW MMC controller at irq 31,32 bit host data width,256 deep fifo [ 25.677154] dwmmc_rockchip ff0d0000.mmc: allocated mmc-pwrseq _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel
